Displaying 3 results from an estimated 3 matches for "targetitinerary".
2013 Dec 20
1
[LLVMdev] extra one cycle of getOperandLatency
Hi llvm-dev,
I wonder why there is an extra cycle for getOperandLatency.
It doesn't seem intuitive.
UseCycle = DefCycle - UseCycle + 1;
When I read the comments in TargetItinerary.td, it said
OperandCycles are optional "cycle counts". They specify the cycle after
instruction issue the values which correspond to specific operand indices
are defined or read.
I thought if an instruction reads the operands at the first cycle
and produces the result at the secon...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
...we could vary the
latency based on which address space pointer register is being used - but
it looks like they're virtual there)
Phil
On Mon, Jun 6, 2016 at 3:10 PM, Ehsan Amiri <ehsanamiri at gmail.com> wrote:
> Hi Phil
>
> There are some comments in "include/llvm/Target/TargetItinerary.td" where
> class InstrItinData is defined.
>
> B is the number of cycles after issue where the first operand of the
> instruction is defined. A is the number of cycles that the instruction will
> stay in that particular stage in the pipeline. So for simple cases, like
> you...
2016 Jun 06
2
Instruction Itineraries: question about operand latencies
In our architecture loads from certain memory locations take a long time to
complete (on the order of 150 clock cycles). Since we don't have a way to
tell at compile time if the address being loaded from lies in slow or fast
memory, I've gone ahead and made all of the load numbers high, such as:
InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>,
However, I see that