search for: targetinstructions

Hello, I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help? Here is the example: I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc I define the instruction TargetInstruction.td as follows: class MyInst <opcode

Hi all, I'm interested in obtaining the cycles spend by the CPU from LLVM and i was wondering if this was possible to obtain this with the scheduling information from LLVM. (For the cortex-m0 in particular). I found the following function : getInstrLatency() in the TargetInstrInfo class. If i sum the latencies of the instructions in a basic block i suppose i will get the total cycle cost