Displaying 2 results from an estimated 2 matches for "targetinstructioninfo".
2011 Jul 21
0
[LLVMdev] backend store i64 on target
...m trying to create new backend. Can anyone help with such question?
In a target there are 32 and 64-bit registers. I've made load/store 32-bit
values without difficulties. Now i'm doing 64-bit store into memory.
There is a direct 64bit store of register -> memory (i represented it in
TargetInstructionInfo.td) and wrote lowering for i64 Constant store.
The question is: does it need to do lowering for i64 register to memory
store or it should "find" this store in TargetInstructionInfo.td?
Thanks in advance.
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2009 Jul 10
2
[LLVMdev] Help: Instruction Pattern Matching question
Hello,
I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help?
Here is the example:
I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc
I define the instruction TargetInstruction.td as follows:...