Displaying 6 results from an estimated 6 matches for "targetinstrimpl".
2013 Sep 22
2
[LLVMdev] how to detect data hazard in pre-RA-sched
hi, LLVM,
I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I
still don't understand how llvm detects data hazard in pre-RA-sched.
pre-RA-sched is based on SDNode and all operands are vregs. Even you can
calculate the operators of SDNodes, the data hazard in vreg are not same as
physical register data hazard. Is it useful to optimize processor pipe...
2013 Sep 24
0
[LLVMdev] how to detect data hazard in pre-RA-sched
On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> hi, LLVM,
>
> I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipe...
2013 Sep 25
2
[LLVMdev] how to detect data hazard in pre-RA-sched
...ister pressure and ILP in
misched.
On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>
> > hi, LLVM,
> >
> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp.
> I still don't understand how llvm detects data hazard in pre-RA-sched.
> pre-RA-sched is based on SDNode and all operands are vregs. Even you can
> calculate the operators of SDNodes, the data hazard in vreg are not same as
> physical register data hazard. Is it useful to opt...
2013 Sep 25
0
[LLVMdev] how to detect data hazard in pre-RA-sched
...anything too terrible either.
> On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>
> > hi, LLVM,
> >
> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipe...
2013 Sep 26
2
[LLVMdev] how to detect data hazard in pre-RA-sched
...right?
On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
>>
>> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>>
>> > hi, LLVM,
>> >
>> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp.
>> I still don't understand how llvm detects data hazard in pre-RA-sched.
>> pre-RA-sched is based on SDNode and all operands are vregs. Even you can
>> calculate the operators of SDNodes, the data hazard in vreg are not same as
>> physical register data hazard. Is...
2013 Sep 26
0
[LLVMdev] how to detect data hazard in pre-RA-sched
...;
>> On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>>
>> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>>
>> > hi, LLVM,
>> >
>> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipe...