search for: targetexternalsymbol

I have noticed that TargetGlobalAddress is generated for "source code" functions and TargetExternalSymbol is generated for builtins like __lshrdi3. What is the difference between TargetExternalSymbol and TargetGlobalAddress? Thanks, Rafael

...r:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t46: ch,glue = callseq_start t0, TargetConstant:i32<0> t47: ch,glue = CopyToReg t46, Register:i64 %reg0, t2 t48: ch,glue = CopyToReg t47, Register:i64 %reg1, t4, t47:1 t50: ch,glue = SHAVEISD::CALL t48, TargetExternalSymbol:i32'__divdi3', Register:i64 %reg0, Register:i64 %reg1, RegisterMask:Untyped, t48:1 t51: ch,glue = callseq_end t50, TargetConstant:i32<0>, TargetExternalSymbol:i32'__divdi3', t50:1 t52: i64,ch,glue = CopyFromReg t51, Register:i64 %reg0, t51:1 t11: ch = CopyToReg t0,...

...nbody.kernel.cu -Xclang -fcuda-is-device -I/home/upitamba/llvm-3.2.src/tools/clang/test/SemaCUDA/ -Xclang -triple -Xclang nvptx64 -Xclang -target-cpu -Xclang sm_10 -S fatal error: error in backend: Cannot select: 0x334a870: v4f32 = NVPTXISD::MoveParam 0x334a770 [ORD=1] [ID=22] 0x334a770: v4f32 = TargetExternalSymbol'.PARAM0' [ID=1] In function: computeBodyAccel Am I doing anything wrong here ? Attached my new nbody.kernel.cu <http://llvm.1065342.n5.nabble.com/file/n56141/nbody.kernel.cu> .cu here -- View this message in context: http://llvm.1065342.n5.nabble.com/UNREACHABLE-executed-err...

...a-is-device > -I/home/upitamba/llvm-3.2.src/tools/clang/test/SemaCUDA/ -Xclang -triple > -Xclang nvptx64 -Xclang -target-cpu -Xclang sm_10 -S > > fatal error: error in backend: Cannot select: 0x334a870: v4f32 = > NVPTXISD::MoveParam 0x334a770 [ORD=1] [ID=22] > 0x334a770: v4f32 = TargetExternalSymbol'.PARAM0' [ID=1] > In function: computeBodyAccel > > Am I doing anything wrong here ? > > Attached my new nbody.kernel.cu > <http://llvm.1065342.n5.nabble.com/file/n56141/nbody.kernel.cu> .cu here > > > > > > > -- > View this message in conte...

Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is

Not really. Clang does not have a way to annotate device vs. kernel functions in C/C++ mode. You're probably better off trying to use OpenCL or CUDA mode in clang. In the clang unit tests, there is a cuda.h header that provides very basic support for these keywords: tests/SemaCUDA/cuda.h If you compile as CUDA (use .cu extension, or "-x cuda") and use this header, you will have

Thanks a lot Justin, I will remove the toolkit header. Just one last question..(maybe ;) ) If I do away with toolkit headers it says unknown type name '__device__'. Does this function qualifier have an alternative ? or I can just do away with ? -- View this message in context: http://llvm.1065342.n5.nabble.com/UNREACHABLE-executed-error-while-trying-to-generate-PTX-tp56026p56093.html

...tAddress = TailCall.getOperand(1); + SDOperand StackAdjustment = TailCall.getOperand(2); + assert ( ((TargetAddress.getOpcode() == ISD::Register && + cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX) || + TargetAddress.getOpcode() == ISD::TargetExternalSymbol || + TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && + "Expecting an global address, external symbol, or register"); + assert( StackAdjustment.getOpcode() == ISD::Constant && "Expecting a const value"); + // TODO: shou...

...\home\Vincent\llvm-2.7\Release\bin\clang.exe File: X86ISelLowering.cpp, Line 2152 Expression: ((Callee.getOpcode() == ISD::Register && (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress) && "Expec clang: error: compiler command failed with exit code 3 (use -v to see invocation) I have attached the preprocessed file (gcc -save-temps) to reproduce. If you need more information, please let me know. -------------- n...

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

...(1); > + SDOperand StackAdjustment = TailCall.getOperand(2); > + assert ( ((TargetAddress.getOpcode() == ISD::Register && > + cast<RegisterSDNode>(TargetAddress)->getReg() == > X86::ECX) || > + TargetAddress.getOpcode() == > ISD::TargetExternalSymbol || > + TargetAddress.getOpcode() == > ISD::TargetGlobalAddress) && > + "Expecting an global address, external symbol, or > register"); > + assert( StackAdjustment.getOpcode() == ISD::Constant && > "Expecting a const valu...

...i32 = Register r3 0x9c08758: <multiple use> 0x9c087e0: <multiple use> 0x9c07388: <multiple use> 0x9c08758: <multiple use> 0x9c08818: ch,flag = CopyToReg 0x9c08758, 0x9c087e0, 0x9c07388, 0x9c08758:1 0x9c08818: <multiple use> 0x9c088a0: i32 = TargetExternalSymbol '__unorddf2' 0x9c085e8: <multiple use> 0x9c08690: <multiple use> 0x9c08720: <multiple use> 0x9c087e0: <multiple use> 0x9c08818: <multiple use> 0x9c088d8: ch,flag = BL 0x9c08818, 0x9c088a0, 0x9c085e8, 0x9c08690, 0x9c08720, 0x9c087e0, 0x9c0...

Hello, Arnold. > with the sentence i tried to express the question whether there is a > way to persuade the code generator to use another register to load (or > move) the function pointer to (right before the callee saved register > restore) but thinking a little further that's nonsense. Why don't define some special op for callee address and custom lower it? I really

On Jul 1, 2008, at 3:42 PM, Richard Osborne wrote: > Evan Cheng wrote: >> On Jun 25, 2008, at 5:13 AM, Richard Osborne wrote: >> >> >>> Evan Cheng wrote: >>> >>>> On Jun 23, 2008, at 5:35 AM, Richard Osborne wrote: >>>> >>>> >>>>> I'm trying to write a backend for a target with no hardware

Evan Cheng wrote: > On Jun 25, 2008, at 5:13 AM, Richard Osborne wrote: > > >> Evan Cheng wrote: >> >>> On Jun 23, 2008, at 5:35 AM, Richard Osborne wrote: >>> >>> >>>> I'm trying to write a backend for a target with no hardware floating >>>> point support. I've added a single i32 register class. I'm

...isTailCall + && IsR3UsedForArgumentPassing + && Subtarget->isThumb1Only() ) + CallAdressShallBeForcedToHardRegR12 = true; + } + // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol // node so that legalize doesn't hack it. @@ -1679,10 +1699,12 @@ bool isLocalARMFunc = false; ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - if (EnableARMLongCalls) { + if (IsCallAddressMoveToRegisterRequired) { assert((Subtarget->isTargetWindows() || +...