search for: targetconfigapass

...ges to incoming IR. GenericScheduler doesn’t magically > solve this problem, but it should never do anything too terrible either. > > Sorry, I have a false statement above. I tried x86/arm/mips and found no misched in use. you means misched is just like a framework. Backend can configure TargetConfigaPass to run misched both pre-RA and post-RA, right? On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote: >> >> > hi, LLVM, >> > >> > I found th...

...changes to incoming IR. GenericScheduler doesn’t magically solve this problem, but it should never do anything too terrible either. > > Sorry, I have a false statement above. I tried x86/arm/mips and found no misched in use. you means misched is just like a framework. Backend can configure TargetConfigaPass to run misched both pre-RA and post-RA, right? It's currently only setup to run pre-RA. I'd like to set it up for post-RA also. I don't expect that to be much work. Backends can configure MI scheduler differently depending on how much control they want. The easiest thing to do is defi...

On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems

Hi, Andrew, Thank you for answering my question. What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 2013 at 4:07 PM,