Displaying 2 results from an estimated 2 matches for "targetcachelevelinfo".
2018 Nov 01
2
RFC: System (cache, etc.) model for LLVM
...entire cache lines,
e.g. dcbz on PowerPC, but it requires the cache line to be correct.
Also see https://www.mono-project.com/news/2016/09/12/arm64-icache/
* Instruction cache
Am Di., 30. Okt. 2018 um 15:27 Uhr schrieb David Greene via llvm-dev
<llvm-dev at lists.llvm.org>:
> class TargetCacheLevelInfo {
> /// getWays - Return the number of ways.
> ///
> unsigned getWays() const;
That is, associativity?
Bandwidth might be a useful addition, e.g. if a performance analysis
tools uses the roofline model.
> class TargetSoftwarePrefetcherInfo {
> /// Should we do...
2018 Nov 01
3
RFC: System (cache, etc.) model for LLVM
...le at
runtime via a hardware register. It supports 3 settings:
* Interpret every memory access as start of a stream
* Interpret a stream when there are 2 consecutive cache misses
* Only establish streams via dcbt instructions.
> >> class TargetMemorySystemInfo {
> >> const TargetCacheLevelInfo &getCacheLevel(unsigned Level) const;
> >>
> >> /// getNumLevels - Return the number of cache levels this target has.
> >> ///
> >> unsigned getNumLevels() const;
> >>
> >> /// Cache level iterators
> >> ///
>...