Displaying 17 results from an estimated 17 matches for "target_vers".
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 2:57 PM, Phil Tomson wrote:
>
>
> I see the following in my SelectCode (in XSTGGenDGISel.inc):
>
>
> /*2235*/ OPC_SwitchOpcode /*2 cases */, 27,
> TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266
> /*2239*/ OPC_RecordChild0, // #1 = $addr
> /*2240*/ OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode,
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
Hello.
I come back to this older thread.
Again, because of i64immSExt32 I receive TableGen error "Could not infer all types
in, pattern!" (exact details written below). So far I'm not able to generate selection
code with TableGen for the ADD_r* instructions, etc:
def i64immSExt32 : PatLeaf<(imm),
[{return
2012 Apr 27
0
[LLVMdev] MemRefs in a Load Instruction
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Pranav Bhandarkar
> Sent: Thursday, April 26, 2012 5:24 PM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] MemRefs in a Load Instruction
>
> Hi,
>
> On the hexagon target, I have written a following combiner pattern.
>
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
Hi Daniel,
Thanks for replying; I was hoping to get in touch with you on this issue.
I had a look at how SelectionIDAG does it when generating the matcher table,
and it does consider the implicit defs as additional output. Here is the
match table generated for the pattern:
/* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND),
/* 3*/ OPC_MoveChild0,
/* 4*/ OPC_CheckOpcode,
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
In an attempt to add vector registers to my target, I ran into a problem.
LLVM started to complain about not being able to infer types from the
provided DAG patterns for several classes of instructions. After a
discussion on the llvm-dev mailing list and IRC channel the recommendation
was to make DAG patterns for these classes of instructions more specific.
Which is what was done. However after
2012 Apr 26
2
[LLVMdev] MemRefs in a Load Instruction
Hi,
On the hexagon target, I have written a following combiner pattern.
*********************************************
def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1,
s11_2ExtPred:$offset1)))),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$src2)))),
(i64 (COMBINE_rr
2014 Nov 05
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
Am 03.11.2014 um 23:30 schrieb Quentin Colombet <qcolombet at apple.com>:
>> Continuing at 4309
>> Match failed at index 4310
>> Continuing at 4322
>> Morphed node: 0x7fef2a033610: i32 = MVrr 0x7fef2a033610 [ORD=21]
>>
>>
>> Does the add operation become a MOVE instruction, or is this a chain of rules?
>
> Yes, your add becomes
2012 Mar 14
2
[LLVMdev] Data/Address registers
Le 07/03/2012 17:36, Jim Grosbach a écrit :
> On Mar 7, 2012, at 6:23 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi Jim,
>>
>> Thanks for your response.
>>
>> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>>> Hi Ivan,
>>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>>
2014 Nov 03
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
>> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same.
>
> And what about view-sched-dags?
The DAG looks like I described below (*)
> This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof!
Here is the dump using the -debug flag. At this point I am not making much
sense of this, would it be too much to ask if one of you could walk me
through one of these lines?
One thing that I didn't point out is that I never defined any separate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at
2012 Mar 14
0
[LLVMdev] Data/Address registers
On Mar 14, 2012, at 7:07 AM, Ivan Llopard wrote:
> Le 07/03/2012 17:36, Jim Grosbach a écrit :
>> On Mar 7, 2012, at 6:23 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi Jim,
>>>
>>> Thanks for your response.
>>>
>>> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>>>> Hi Ivan,
>>>> On Mar 3,
2012 Mar 07
0
[LLVMdev] Data/Address registers
On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi Jim,
>
> Thanks for your response.
>
> Le 06/03/2012 22:54, Jim Grosbach a écrit :
>> Hi Ivan,
>> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>>
>>> Hi,
>>>
>>> I'm facing a problem in llvm while porting it
2012 Mar 07
2
[LLVMdev] Data/Address registers
Hi Jim,
Thanks for your response.
Le 06/03/2012 22:54, Jim Grosbach a écrit :
> Hi Ivan,
> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote:
>
>> Hi,
>>
>> I'm facing a problem in llvm while porting it to a new target and I'll
>> need some support.
>> We have 2 kind of register, one for general purposes (i.e.
2016 Feb 22
2
Failure to match a DAG after a minor pattern change in a custom Target
On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote:
>
>> [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
>> immSExt16:$imm), (i32 Cond)))]> {
>>
>
> I suspect that the "set SR:$rD" is the problem here. The Esenciasetflag
2014 Mar 08
2
[LLVMdev] Isel DAG documentation?
On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote:
> ISDOpcodes.h contains what documentation there is on the semantics of each
> opcode.
And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in
MachineInstr form, but you'll see them with -view-sched-dags, and
occasionally before).
Tim.
2014 Mar 09
2
[LLVMdev] Isel DAG documentation?
Hi David,
> [(set GR32:$rD, globaladdr:$addr)]
> It seems to have somehow managed to create a cycle in the DAG, which is
> of course wrong. But how?
When I write a similar pattern into the ARM .td files and look at
(from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see:
/*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494
/*56481*/