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On 1/15/2016 2:57 PM, Phil Tomson wrote: > > > I see the following in my SelectCode (in XSTGGenDGISel.inc): > > > /*2235*/ OPC_SwitchOpcode /*2 cases */, 27, > TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266 > /*2239*/ OPC_RecordChild0, // #1 = $addr > /*2240*/ OPC_MoveChild, 0, > /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress), > /*2245*/ OPC_MoveParent, > /*2246*/ OPC_MoveParent, > /*2247*...

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

...above pattern where in the LDriw (the second load in the COMBINE_rr) is changed to LDriw_indexed similar to the first load. I see the following in HexagonGenDAGISel.inc *********************************************** /*1161*/ OPC_EmitConvertToTarget, 2, /*1163*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed), 0|OPFL_Chain, 1/*#VTs*/, MVT::i32, 2/*#Ops*/, 1, 6, // Results = #7 /*1172*/ OPC_EmitConvertToTarget, 5, /*1174*/ OPC_EmitNode, TARGET_VAL(Hexagon::LDriw_indexed), 0|OPFL_Chain, 1/*#VTs*/, MVT::i32,...

...Thanks for replying; I was hoping to get in touch with you on this issue. I had a look at how SelectionIDAG does it when generating the matcher table, and it does consider the implicit defs as additional output. Here is the match table generated for the pattern: /* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND), /* 3*/ OPC_MoveChild0, /* 4*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL), /* 7*/ OPC_MoveChild0, /* 8*/ OPC_CheckOpcode, TARGET_VAL(ISD::ANY_EXTEND), /* 11*/ OPC_RecordChild0, // #0 = $src /* 12*/ OPC_CheckChild0Type, MVT::i16, /* 14*/ OPC_MoveParent,...

On 1/15/2016 1:08 PM, Phil Tomson wrote: > > Ah, I see, the defm is a multi-class so I needed to change it to: > > def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)), > (LOADI64_RI tglobaladdr:$addr, 0)>; > // Match load from a relocatable address to a load with GRP: > def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)), > (LOADI64_RI

In an attempt to add vector registers to my target, I ran into a problem. LLVM started to complain about not being able to infer types from the provided DAG patterns for several classes of instructions. After a discussion on the llvm-dev mailing list and IRC channel the recommendation was to make DAG patterns for these classes of instructions more specific. Which is what was done. However after

Hi, On the hexagon target, I have written a following combiner pattern. ********************************************* def: Pat<(i64 (or (i64 (shl (i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset1)))), (i32 32))), (i64 (zextloadi32 ADDRriS11_2:$src2)))), (i64 (COMBINE_rr

...ules? > > Yes, your add becomes a MVrr instruction. This is likely the problem. > Do you know how to debug this, or do you want me to give you basic directions? I had a look at the matcher table and it looks as follows: /*4309*/ /*Scope*/ 12, /*->4322*/ /*4310*/ OPC_CheckOpcode, TARGET_VAL(MBPISD::RET_FLAG), /*4313*/ OPC_RecordNode, // #0 = 'retflag' chained node /*4314*/ OPC_CaptureGlueInput, /*4315*/ OPC_EmitMergeInputChains1_0, /*4316*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::RETL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0, 0/*#VTs*/, 0/*#Ops*...

...rns have the same complexity and they are located at different scopes. For these two patterns, tblgen is producing the following isel opcodes: /*3244*/ /*Scope*/ 20, /*->3265*/ /*3245*/ OPC_RecordChild1, // #1 = $b /*3246*/ OPC_MoveChild, 1, /*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant), /*3251*/ OPC_MoveParent, /*3252*/ OPC_CheckType, MVT::i16, /*3254*/ OPC_EmitConvertToTarget, 1, /*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0, and in the same logic chain of pattern checking, DADDri comes right after AADDMri (with Scope changes i...

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

Thanks Anton and Krzysztof! Here is the dump using the -debug flag. At this point I am not making much sense of this, would it be too much to ask if one of you could walk me through one of these lines? One thing that I didn't point out is that I never defined any separate floating point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at

...exity and they are located at different scopes. For these two patterns, tblgen is producing the following isel opcodes: > > /*3244*/ /*Scope*/ 20, /*->3265*/ > /*3245*/ OPC_RecordChild1, // #1 = $b > /*3246*/ OPC_MoveChild, 1, > /*3248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant), > /*3251*/ OPC_MoveParent, > /*3252*/ OPC_CheckType, MVT::i16, > /*3254*/ OPC_EmitConvertToTarget, 1, > /*3256*/ OPC_MorphNodeTo, TARGET_VAL(ME::AADDMri), 0, > > and in the same logic chain of pattern checking, DADDri comes right after...

On Mar 7, 2012, at 6:23 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi Jim, > > Thanks for your response. > > Le 06/03/2012 22:54, Jim Grosbach a écrit : >> Hi Ivan, >> On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: >> >>> Hi, >>> >>> I'm facing a problem in llvm while porting it

Hi Jim, Thanks for your response. Le 06/03/2012 22:54, Jim Grosbach a écrit : > Hi Ivan, > On Mar 3, 2012, at 4:48 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: > >> Hi, >> >> I'm facing a problem in llvm while porting it to a new target and I'll >> need some support. >> We have 2 kind of register, one for general purposes (i.e.

...ging info shows correspond to > the numbers in that file. Here's an example from HexagonGenDAGISel.inc: > > /*28*/ OPC_Scope, 88|128,3/*472*/, /*->503*/ // 3 children in > Scope > /*31*/ OPC_MoveChild, 1, > /*33*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD), > /*36*/ OPC_RecordChild0, // #2 = $base > /*37*/ OPC_RecordChild1, // #3 = $offset > /*38*/ OPC_MoveChild, 1, > /*40*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant), > /*43*/ OPC_Scope, 65, /*->110...

On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote: > ISDOpcodes.h contains what documentation there is on the semantics of each > opcode. And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in MachineInstr form, but you'll see them with -view-sched-dags, and occasionally before). Tim.

...D, globaladdr:$addr)] > It seems to have somehow managed to create a cycle in the DAG, which is > of course wrong. But how? When I write a similar pattern into the ARM .td files and look at (from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see: /*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494 /*56481*/ OPC_RecordNode, // #0 = $src /*56482*/ OPC_CheckType, MVT::i32, /*56484*/ OPC_CheckPatternPredicate, 4, // (!Subtarget->isThumb()) /*56486*/ OPC_MorphNodeTo, TARGET_VAL(ARM::MOVi32imm), 0, 1/*#VTs*/, MVT::i32, 1/*#Ops*...