search for: tailrecurse

...preds = %0 ret i32 %n } You see that the tail call is not eliminated. However, it does get eliminated if I change to this code: unsigned int fib(unsigned int n) { return n <= 2 ? 1 : fib(n-1) + fib(n-2); } IR: define i32 @_Z9fibj(i32 %n) #0 { %1 = icmp ult i32 %n, 3 br i1 %1, label %tailrecurse._crit_edge, label %tailrecurse tailrecurse: ; preds = %0, %tailrecurse %n.tr2 = phi i32 [ %4, %tailrecurse ], [ %n, %0 ] %accumulator.tr1 = phi i32 [ %5, %tailrecurse ], [ 1, %0 ] %2 = add i32 %n.tr2, -1 %3 = tail call i32 @_Z9fibj(i32 %2) %4 = add i3...

...ry, Since we originally had this discussion, and I got thoroughly confused, LLVM has moved on. The answer is now _yes_ on both points. If you compile the function above with the 1.1 (or later) compiler, you should get something like this: int %rec_func(int %x, int %y) { entry: br label %tailrecurse tailrecurse: ; preds = %entry, %endif %cann-indvar = phi uint [ 0, %entry ], [ %next-indvar, %endif ] ; <uint> [#uses=2] %accumulator.tr = phi int [ %x, %entry ], [ %tmp.9, %endif ] ; <int> [#uses=2] %cann-indvar = cast uint %cann-i...

...le: //------------ int f(int n) { if(n<2) return 1; return f(n-1) + f(n-2); } //------------ in this LLVM byte code output: --------------------------------------------------- target endian = little target pointersize = 32 implementation ; Functions: int %f(int %n) { entry: br label %tailrecurse tailrecurse: ; preds = %entry, %endif %cann-indvar = phi uint [ 0, %entry ], [ %next-indvar, %endif ] ; <uint> [#uses=2] %accumulator.tr = phi int [ 1, %entry ], [ %tmp.9, %endif ] ; <int> [#uses=2] %cann-indvar = cast uint %cann-indvar to int ; <int> [#uses=1] %n.tr-scal...

Hello again Valery, Valery A.Khamenya wrote: > All benefits, what one could obtain from "LLVM supporting multiple CPU > at single host", one might obtaine from "LLVM supporting multiple CPU > at multiple hosts". Isn't that logical? I see more precisely what you mean, but I don't think it is that straightforward to generalise the benefits multiple CPU on

> Interesting email address there :) > On Thu, 2004-01-08 at 01:18, =?koi8-r?Q?=22?=Valery > A.Khamenya=?koi8-r?Q?=22=20?= wrote: unfortunally some email parsers and email clients deny to work correctly with international conventions :( follow this URL for more details: http://www.python.org/doc/current/lib/module-email.Header.html > On the same machine, LLVM definitely needs to

...e LLVM, I tried this code: int sum(int n) { if (n == 0) return 0; else return n + sum(n-1); } and this is what "llvm-gcc -O2" gave me: define i32 @sum(i32 %n) nounwind { entry: %tmp215 = icmp eq i32 %n, 0 ; <i1> [#uses=1] br i1 %tmp215, label %bb10, label %tailrecurse.bb10_crit_edge tailrecurse.bb10_crit_edge: ; preds = %entry %tmp = add i32 %n, -1 ; <i32> [#uses=3] %tmp17 = mul i32 %tmp, %tmp ; <i32> [#uses=1] %tmp18 = add i32 %tmp17, %n ; <i32> [#uses=1] %tmp. = zext i32 %tmp to i64 ; <i64> [#uses=2] %tmp19 = add i64 %tmp., -...