search for: tailmerg

Hi everyone, The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. I did an experiment of adding additional BranchFolding and BlockPlacement after the existing BlockPlacement (i.e., -bloc...

Hi, I am building llvm 3.3 with cmake on PPC64 and have a bunch of regression test failures. With only PPC backend enabled the list of failures is: [ 1553s] Failing Tests (20): [ 1553s] LLVM :: CodeGen/PowerPC/2007-05-22-tailmerge-3.ll [ 1553s] LLVM :: CodeGen/PowerPC/2007-09-08-unaligned.ll [ 1553s] LLVM :: CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll [ 1553s] LLVM :: CodeGen/PowerPC/available-externally.ll [ 1553s] LLVM :: CodeGen/PowerPC/branch-opt.ll [ 1553s] LLVM :: CodeGen/PowerPC/stubs.ll [ 1553s]...

...mez <ismail at donmez.ws> wrote: > Hi, > > I am building llvm 3.3 with cmake on PPC64 and have a bunch of regression > test failures. With only PPC backend enabled the list of failures is: > > [ 1553s] Failing Tests (20): > [ 1553s] LLVM :: CodeGen/PowerPC/2007-05-22-tailmerge-3.ll > [ 1553s] LLVM :: CodeGen/PowerPC/2007-09-08-unaligned.ll > [ 1553s] LLVM :: CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll > [ 1553s] LLVM :: CodeGen/PowerPC/available-externally.ll > [ 1553s] LLVM :: CodeGen/PowerPC/branch-opt.ll > [ 1553s] LLVM :: CodeGen/Pow...

...etely* wrong here. CodeGen correctly preserves the ordering of blocks from IR, *unless* it can do folding, etc. That's right. However, the CFG changes quite a bit during CodeGen. Switches can be lowered into branch trees, multiple passes can split critical edges, and then there is taildup and tailmerge. An IR code layout algorithm simply doesn't know the final CFG. > As for why it should be an IR pass, mostly because once the selection dag runs through the code, we can never recover all of the freedom we have at the IR level. To start with, splicing MBBs around requires known about the...

On Tue, Oct 18, 2011 at 2:59 PM, Cameron Zwarich <zwarich at apple.com> wrote: > On Oct 18, 2011, at 2:53 AM, Chandler Carruth wrote: > > > Hello, > > > > I'm working on basic-block placement optimizations based on branch > probability information. I've run into a stumbling block though. One of the > existing passes to do this, essentially a dead pass

...blem with this section of code is that FallThrough is not guaranteed to be a successor of MBB or even a descendent of MBB. The bitcode I've attached is a case where there are 5 basic blocks, where the first four end with conditional branches to an early return, as specified with initial.dot. TailMergeBlocks in BranchFolding::runOnMachineFunction merges the 4 early return blocks to a single basic block and numbers renumbers them, as specified with tailmerge.dot. When it runs optimize block on the if.end14 block, it enters the above segment of code, removing it and replacing it with FallThrough,...

...tly > preserves the ordering of blocks from IR, *unless* it can do folding, etc. > > > That's right. However, the CFG changes quite a bit during CodeGen. > > Switches can be lowered into branch trees, multiple passes can split > critical edges, and then there is taildup and tailmerge. > > An IR code layout algorithm simply doesn't know the final CFG. > To be clear, I don't disagree with any of this. =] However, my rough experiments thus far (hoping to have real benchmark data soon) seem to indicate that just giving a baseline ordering of block to the CodeGen...

...en/Generic/select.ll LLVM : : CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll LLVM : : CodeGen/PowerPC/2006-09-28-shift_64.ll LLVM : : CodeGen/PowerPC/2007-03-30-SpillerCrash.ll LLVM : : CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll LLVM : : CodeGen/PowerPC/2007-05-22-tailmerge-3.ll LLVM : : CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll LLVM : : CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll LLVM : : CodeGen/PowerPC/2007-11-16-landingpad-split.ll LLVM : : CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll LLVM : : CodeGen/PowerPC/2008-03-05-RegS...