Displaying 3 results from an estimated 3 matches for "taddrspi".
2019 May 28
2
Instruction is selected, but it shouldn't (?)
...probably the general-register version), and only specify a pattern for that one.
>
> For computing the addresses of stack slots in particular, you might want to look at how the ARM backend generates Thumb1 code. Thumb1 has special instructions for SP-relative accesses (tADDframe, tADDrSP, tADDrSPi, tLDRspi, tSTRspi). Explicit copies from “sp” don’t really come up during isel, except for call arguments; most of the interesting code is part of frame lowering.
>
> -Eli
>
> From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev
> Sent:...
2019 May 28
2
Instruction is selected, but it shouldn't (?)
In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:
def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;
The SP can not be used in general purpose arithmetic instructions, therefore I defined the following
2012 Aug 23
0
[LLVMdev] % in tablegen
...ng register. Is there any way to make tablgen ignore the %? I have
tried '\' character, and two "%%". None worked.
// ADD <Rd>, sp, #<imm8>
// This is rematerializable, which is particularly useful for taking the
// address of locals.
let isReMaterializable = 1 in
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs),
IIC_iALUi,
"add\t$dst, %prefix_$sp, $rhs", []>,
T1Encoding<{1,0,1,0,1,?}> {
// A6.2 & A8.6.8
bits<3> dst;
bits<8> rhs;
let Inst{10-8} = dst;
let Inst{7-0} = rhs;...