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Hi folks, It took a while, but I finally have some bandwidth to look at this. I've been reading the two existing TableGen documents: http://llvm.org/docs/TableGenFundamentals.html http://llvm.org/docs/TableGen/LangRef.html the first is linked from the index, but LangRef is not (though it has some remains in the metadata). I'm wondering what's the relationship between them two. My plan is to have three docs: 1. What is TableGen; No info about language, back-en...

All, Where are the SSE instructions defined? Specifically, I cannot find the def for ADDSDrr. Aran -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 194 bytes Desc: This is a digitally signed message part. URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100326/130b2e02/attachment.sig>

...u are starting a new port, we recommend that you write the > instruction selector using the SelectionDAG infrastructure." > > any other things i should know before i write one? You should read these: http://llvm.cs.uiuc.edu/docs/WritingAnLLVMBackend.html http://llvm.cs.uiuc.edu/docs/TableGenFundamentals.html If you're unsure of how things are implemented, take a look at how similar things are done in X86, PowerPC, Alpha or IA64, they all have SelectionDAG-based instruction selectors (*ISelPattern.cpp). If that doesn't clear things up, ask on the list or IRC channel. -- Misha Brukman ::...

...gt; To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu) > Subject: Re: [LLVMdev] Tablegen foreach > > I think a multiclass may be a better fit for what you are trying to > do. In fact, this is the canonical example for multiclasses: > <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions- > and-instances>. > > --Sean Silva > > On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: > > I'm trying to find examples of the foreach pattern being used in > tablegen > > files. > >...

...nnot find any document on initializing the 'dag' type variable, > and I cannot understand the syntax of "asmstring" either. The DAG operator is just a nested set of parens, e.g. (X (Y Z), Q), where X,Y,Z,Q are tblgen defs. This is described here: http://llvm.cs.uiuc.edu/docs/TableGenFundamentals.html#values > how does the x86 asmwrite interpret the "AsmString" ? The X86 has two asm formats: Intel and AT&T. Things in {}'s get split up and treated as one or the other. The 0 part is AT&T, the 1th part is Intel. It might make it more clear to just say that this...

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I’m trying to find examples of the foreach pattern being used in tablegen > files. > > The problem I am trying to solve is to simplify t...

...n initializing the 'dag' type variable, > > and I cannot understand the syntax of "asmstring" either. > > The DAG operator is just a nested set of parens, e.g. (X (Y Z), Q), where > X,Y,Z,Q are tblgen defs. This is described here: > http://llvm.cs.uiuc.edu/docs/TableGenFundamentals.html#values > > > how does the x86 asmwrite interpret the "AsmString" ? > > The X86 has two asm formats: Intel and AT&T. Things in {}'s get split up > and treated as one or the other. The 0 part is AT&T, the 1th part is > Intel. It might make it more...

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the

I'm trying to find examples of the foreach pattern being used in tablegen files. The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal. So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations. Instead of writing all the combinations out, I'd like to use

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

...>> Cc: llvmdev at cs.uiuc.edu (LLVMdev at cs.uiuc.edu) >> Subject: Re: [LLVMdev] Tablegen foreach >> >> I think a multiclass may be a better fit for what you are trying to >> do. In fact, this is the canonical example for multiclasses: >> <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions- >> and-instances>. >> >> --Sean Silva >> >> On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> >> wrote: >> > I'm trying to find examples of the foreach pattern being used in >> table...

...registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, > which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? No examples I know of, but I don't think there should be any issues using multiclass, as long as there aren't too many possible modifiers; see http://llvm.org/docs/TableGenFundamentals.html and various uses in the code for how that works. -Eli

So, I have this small test program that I figured would cause no problems but want to test all the various data types and operations with my modified sparc backend. I've been working on LLVM for about 3 days now, so this might be a problem with not knowing enough yet, so thanks for bearing with me. The code that I based my example off of is compiled to LLVM-IR from: void

...registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, > which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? No examples I know of, but I don't think there should be any issues using multiclass, as long as there aren't too many possible modifiers; see http://llvm.org/docs/TableGenFundamentals.html and various uses in the code for how that works. Thanks, I'll go back to that and see if I can get it to work how I want. -Eli _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mai...

...VM, consider reading some documents and looking at some of the presentations here: http://llvm.org/docs/#llvmdesign . You can also see how other backends are implemented in LLVM: http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ . You'll want to read about Tablegen: http://llvm.org/docs/TableGenFundamentals.html which will tell you how to write the .td files to describe your target, and then write the correct components (code generator, assembly printer, etc.) for your target. Good luck! Misha -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/p...

...sses. Now I wonder whether it is better to use tablegen to generate the Haskell code. The tblgen man page says, that tablegen emits C++. This would not be a big problem, since I could let it write C++ code that in turn writes Haskell code. Unfortunately the section "http://llvm.org/docs/TableGenFundamentals.html#backends" is not yet written. Is it possible to use the llvm-tblgen binary without modification or do I have to extend llvm-tblgen or do I have to write my own C++ code that uses some of the functions from the tblgen library? Are there any (simple) examples of custom tblgen backends...

As the first tentative step towards documenting the LLVM code generator (and generally closing one of the massive holes in the dox), I just wrote up the "TableGen Fundamentals" document, and uploaded it here: http://llvm.cs.uiuc.edu/docs/TableGenFundamentals.html This describes the basic idea behind TableGen, the type system and expression syntax it uses, why it's useful, etc. If you are interested in TableGen or the LLVM code generator, I would recommend taking a look at it, then sending me feedback. :) The current plan is to continue to flesh...

...c.edu/pipermail/llvm-commits/Week-of-Mon-20060828/037344.html More could be done in the sparc backend if desired, such as factoring out commonality between the float and double patterns, etc, but this isn't a super high priority for me :). The feature is described here: http://llvm.org/docs/TableGenFundamentals.html#multiclass -Chris -- http://nondot.org/sabre/ http://llvm.org/

...orementioned prototype for each one of the backends and all of the backends can be their own nicely self-contained .cpp file. Clang has its own backends, but the makeover would be identical. I'll also take the opportunity to fill in the sorely needed TODO at the end of <http://llvm.org/docs/TableGenFundamentals.html>. Finally :))))) Finally, does anyone foresee me needing to make any changes to be build system? If so, some advice would be appreciated. Any objections? --Sean Silva -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-...

..."mov{b} {$src, $dst|$dst, $src}", []>, isSameSize($dst, > $src); We already have something like this, but it's a little more general. The X86 backend hasn't been converted to use it. This is the 'multiclass' facility in tblgen: http://llvm.org/docs/TableGenFundamentals.html#multiclass Basically this lets you use one definition to implement multiple different instructions. For example, most instructions in the sparc target come in "reg,reg" and "reg,imm" forms. As such, it defines: multiclass F3_12<string OpcStr, bits<6> Op3Val,...