search for: tablegen'erated

Helper function: template<typename InsnType> static InsnType fieldFromInstruction(InsnType insn, unsigned startBit, unsigned numBits) { assert(startBit + numBits <= (sizeof(InsnType)*8) && "Instruction field out of bounds!"); InsnType fieldMask; if (numBits == sizeof(InsnType)*8) fieldMask =

...I think we don't even have a bug open for this, but it has been brought up) Unrelated to O0, here are some pending patches (at least that I'm aware of): * Legalization of non-power-of-2 types [5] - this hasn't seen any activity in a while, but it would be nice to move forward with it * TableGen for the instruction selector: support for predicates [6] - needs a rebase, would be very useful for ARM * Formatting TableGen'erated files [7] - this is an older patch and it doesn't really need to be limited only to GlobalISel, it looks like it might be a good idea for TableGen in general...

...ve register constraints (like x86 8bit operations only work on > al,ah,etc.) then you have to create a new register class to express that. > (The only exception being limited to a single register, which instead we > express by assigning the physreg directly instead of using a vreg). > - Tablegen may create more regsiter classes for register coalescing where > we want to accomodate constraints of multiple instructions at the same time. > - All the information is in the .td file; you just have to put some effort > into learning tablegen as the information is often expressed by using...

...also have some in Phab. For those of you that are interested, please have a look at the following topics - discussions are progressing rather slowly and we definitely wouldn't mind some more involvement from the community: Legalization of non-power-of-2 types: https://reviews.llvm.org/D30529 TableGen for the instruction selector (last pass in the GlobalISel pipeline): https://reviews.llvm.org/D31418 and the rest of its stack We have also set up a sort of scratchpad document here: https://goo.gl/IS2Bdw At the moment it contains mostly notes from the BoF and a few other emails. The intention is...

...he ISA would mean some instructions are enabled or disabled based on one of a set of features being enabled, and such a feature might be useful to other backends too. I have implemented a prototype of this extension in https://reviews.llvm.org/D74338. AssemblerPredicates are used in four parts of TableGen, three of which only affect TableGen'erated code, and one is RISC-V specific so these changes are not very intrusive. For AsmWriterEmitter/MCInstPrinter to work with these changes, I've made what I think may be a minimally distruptive change, but I'm happy to hear any alternative ideas...

Hello everyone, I noticed that there are several register classes defined in X86 target and many of them are overlapping. Is there a list of all X86 register classes documented somewhere? I found many listed in X86GenRegisterInfo.inc(generated by tablegen) but unsure if that is the complete list. Also, is there documentation on the role and purpose of these classes and how the X86 backend decides which class to choose when generating machine code? The comments in X86RegisterInfo.td didn't help much to fully understand and I wasn't sure where...