search for: t9_64

...Scheduler.Observe(MI, CurrentCount); (gdb) p (*MBB).dump()* * BB#218: derived from LLVM BB %if.then1289 Live Ins: %A2 %S0_64 %S1_64 %S2_64 %S4 %S5_64 %T0 %T1 %T2 %T3_64 %T6 %T8 %T9 Predecessors according to CFG: BB#217 ... %V0<def> = ADDu %ZERO, %T9<kill> %T9_64<def> = LD_P8 %T3_64, <ga:@intrapred>[TF=3]; mem:LD8[GOT] ... JALR64 %T9_64<kill>, %A0_64<kill>, %A1<kill>, %A2<kill>, %A3<kill>, %T0<kill>, <regmask>, %SP<imp-def>, %V0<imp-def> ... BNE %V0, %V1, <BB#372> * MI...

Hi Akira, > I am running into a problem when I turn on post-RA scheduler with mode > "ANTIDEP_CRITICAL" for mips. > I'd appreciate if someone could explain what is going wrong here. All these passes are pretty sensitive to correct register liveness information. As a first step I'd check whether machine verifier reports no errors here. -- With best regards, Anton

...elay slots, not because it has detected any true violations. $ llc macroblock.llvm.mips64el.ll -mcpu=mips64r2 -O3 -o macroblock.s -mattr=n64 -verify-machineinstrs # After PreEmit passes # Machine code for function start_macroblock: Post SSA BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %T9_64 %RA_64 %S3_64 %S2_64 %S1_64 %S0_64 BEQ %A0<kill>, %ZERO, <BB#2> NOP Successors according to CFG: BB#2 BB#1 # End machine code for function start_macroblock. *** Bad machine code: MBB exits via unconditional fall-through but doesn't have exactly one CFG successor! *** -...