Displaying 20 results from an estimated 127 matches for "t9".
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...G: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...G: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...es:
>> t0: ch = EntryToken
>> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
&g...
2017 Aug 10
4
PROC MIXED RANDOM equivalence in R nlme
...;m
unable to provide an example.
The original SAS v6.12 code is provided below:
------------------------------------------------------------------
/* READ DATA */
DATA emiss;
INFILE 'data.tab' LRECL=8000 FIRSTOBS=2 DLM='09'X MISSOVER DSD;
INPUT study $ vehicle $ thc rv t5 t9 ar ol ox su bz;
/* CREATE NEW VARIABLES */
ln_thc = log (thc);
new = study||vehicle;
/* PERFORM ANALYSIS */
PROC MIXED DATA=emiss MAXITER=1000 CONVH=1E-8 METHOD=REML NOCLPRINT
NOITPRINT;
CLASS new;
MODEL ln_thc = rv t5 t9 ar ol ox su bz
/S DDFM=RES;
RANDOM int rv t5...
2006 Apr 27
2
as.factor: changed behaviour for Date class
Dear all,
I have noticed a little change in the behaviour of as.factor from R-2.2.1 to
R-2.3.0, and can't find it in the NEWS.
In R-2.3.0:
> times <- 1:5
> class(times) <- "Date"
> as.factor(times)
[1] 1 2 3 4 5
Levels: 1 2 3 4 5
In R-2.2.1:
> as.factor(times)
[1] 1970-01-02 1970-01-03 1970-01-04 1970-01-05 1970-01-06
Levels: 1970-01-02 1970-01-03 1970-01-04
2006 Apr 27
2
as.factor: changed behaviour for Date class
Dear all,
I have noticed a little change in the behaviour of as.factor from R-2.2.1 to
R-2.3.0, and can't find it in the NEWS.
In R-2.3.0:
> times <- 1:5
> class(times) <- "Date"
> as.factor(times)
[1] 1 2 3 4 5
Levels: 1 2 3 4 5
In R-2.2.1:
> as.factor(times)
[1] 1970-01-02 1970-01-03 1970-01-04 1970-01-05 1970-01-06
Levels: 1970-01-02 1970-01-03 1970-01-04
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
> t6: i64 = sub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>
> Combining: t13: ch = XSTGISD::Ret t12, Regist...
2017 Aug 11
0
PROC MIXED RANDOM equivalence in R nlme
...t;
> The original SAS v6.12 code is provided below:
>
> ------------------------------------------------------------------
> /* READ DATA */
> DATA emiss;
> INFILE 'data.tab' LRECL=8000 FIRSTOBS=2 DLM='09'X MISSOVER DSD;
> INPUT study $ vehicle $ thc rv t5 t9 ar ol ox su bz;
>
> /* CREATE NEW VARIABLES */
> ln_thc = log (thc);
> new = study||vehicle;
>
> /* PERFORM ANALYSIS */
> PROC MIXED DATA=emiss MAXITER=1000 CONVH=1E-8 METHOD=REML NOCLPRINT
> NOITPRINT;
> CLASS new;
>
> MODEL ln_thc = rv t5 t9 ar ol ox su bz
>...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...hen when i use the
> command -view-dag-combine2-dags i get the required output in graph
> but the following error on console:
>
> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x
> i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7,
> t12, undef:i64
> t7: v64i32 = add t6, t4
> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
> undef:i64
> t14: i64 = X86ISD::Wrapper TargetGloba...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...vm. then when i use the command -view-dag-combine2-dags i
>> get the required output in graph but the following error on console:
>>
>> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a
>> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>> t7: v64i32 = add t6, t4
>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[6...
2009 Mar 18
1
Reading a file line by line - separating lines VS separating columns
...s, to
which I found a solution but it doesn't feel to be a smart solution, any
ideas or help of how to improve this would be welcomed.
# sample code:
# creating a simple file zz <- file("ex.data", "w") # open an output file
connection cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") cat( "1\t2\t3\t4\t5\t6\t7\t8\t9\t10\t\t555\t\t", file = zz, sep =
"\n") (temp.file = scan("ex.data", what = "",...
2007 Jun 22
1
Nuance Buys Tegic from AOL for $265m
Nuance Communications has agreed to buy Tegic Communications, the
developer of the T9 predictive text input software for mobile phones,
from AOL for $265 million in cash.
http://www.wirelessweek.com/article.aspx?id=149702
Article goes on to say T9 is in use on over 2.5billion phones - wow now
that's a patent worth filing.
Regards,
Dean Collins
Cognation Pty Ltd
d...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...ions. I will pick and choose debug output to keep this small.
SelectionDAG has 36 nodes:
t0: ch = EntryToken
t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
t4: i32 = or t2, Constant:i32<256>
t9: i32 = shl t4, Constant:i32<2>
t10: i32 = add t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
t16: ch = llvm.tpu.dma.write.1KB.async t0,
TargetConstant:i32<4602>, t10, t12, t15
t18: i...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...>>
>> SelectionDAG has 36 nodes:
>> t0: ch = EntryToken
>> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
>> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
>> t4: i32 = or t2, Constant:i32<256>
>> t9: i32 = shl t4, Constant:i32<2>
>> t10: i32 = add t6, t9
>> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
>> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
>> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>...
2010 Jun 03
5
string handling
I have a data.frame as the following:
var1 var2
9G/G09 abd89C/T90
10A/T9 32C/C
90G/G A/A
. .
. .
. .
10T/C 00G/G90
What I want is to get the letters which are on the left and right of '/'.
for example, for "9G/G09", I only want "G", "G", and for "abd89C/T90", I
onl...
2012 Aug 29
4
Sorting of columns of a matrix
Dear all,
Please suggest me how can I do it.
I have a matrix which look like following:
x1 x2 x3 t1 .01 0.3 0 t2 0 0.1 0.01 t3 0 .01 .01 t4 0 0 t5 5 0 0 t6
0 0 0 t7 0 0 0 t8 0 0 0 t9 0.6 0 0 t10 0 0 0.66 t11 0 0.6 0.11 t12 0
0.4 0
I want to sort decreasing order in each column based on rows. and then to
display only those rows which has a value. The expected out put matrix will
look like
x1 x2 x3 t9 0.6 t11 0.6 t10 0.66 t1 .01 t12 0.4 t11 0.11 t1 0.3 t2 .01
t2 0.1...
2010 Jul 23
2
start and end times to yes/no in certain intervall
...;, "13:00", "13:00", "13:00", "13:00", "13:00",
"13:00", "13:00")), .Names = c("start", "end"), row.names = c(NA,
20L), class = "data.frame")
and I would like the data to look like this:
> t9 t10 t11 t12 t13 t14 t15 t16 t17
> 1 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 2 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 3 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 4 FALSE FALSE TRUE FALSE FALSE FALSE FALSE FALSE FALSE
>...
2013 Sep 17
1
[LLVMdev] [llvm] r190328 - Revert patches to add case-range support for PR1255.
...h for Mips16 llvm which works around the issue for now.
In general, pure risc architectures have no pity for compiler and
toolchain developers. Mips16 is way more extreme in this way than mips32.
In mips32, there is no PC register or PC relative instructions.
To make PIC work, they load register T9 with the address of the function
that is being called.
For referencing the GOT then, you have to emit this two sequence
instruction as the first two instructions of the function so that this
T9 register can be used to load from the GOT.
In mips16 there is no PC register either but there are so...
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
...X "MipsCompilationCallback\n"
ASMPREFIX "MipsCompilationCallback:\n"
".ent " ASMPREFIX "MipsCompilationCallback\n"
- ".frame $sp, 32, $ra\n"
+ ".frame $29, 32, $31\n"
".set noreorder\n"
- ".cpload $t9\n"
+ ".cpload $25\n"
- "addiu $sp, $sp, -64\n"
+ "addiu $29, $29, -64\n"
".cprestore 16\n"
// Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
@@ -115,35 +115,35 @@
// concerned. We also need to save the...
2010 Mar 10
1
PCA
Hello,
I am trying to complete a PCA on a set of standardized ring widths from 8
different sites (T10, T9, T8, T7, T6, T5, T3, and T2).
The following is a small portion of my data:
T10 T9 T8 T7 T6 T5 T3 T2 1.33738 0.92669 0.91146 0.98922 0.9308 0.88201
0.92287 0.91775 0.82181 1.05319 0.92908 0.97971 0.95165 0.98029 1.14048
0.77803 0.88294 0.96413 0.90893 0.87957 0.9961 0.74926 0.71394 0.70877
1.07549...