Displaying 3 results from an estimated 3 matches for "t83".
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2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...x i32>
<i32 2, i32 2, i32 2, i32 2>
%t78 = fmul <4 x float> %t63, %t76
%t79 = fadd <4 x float> %t75, %t78
%t80 = shufflevector <4 x float> %t50, <4 x float> undef, <4 x i32>
<i32 3, i32 3, i32 3, i32 3>
%t82 = fmul <4 x float> %t67, %t80
%t83 = fadd <4 x float> %t79, %t82
ret <4 x float> %t83
}
Before D70246, opt -instcombine gives this:
define <4 x float> @f(i32 %t32, <4 x float>* %t24) {
.entry:
%t43 = insertelement <3 x i32> undef, i32 %t32, i32 2
%t44 = bitcast <3 x i32> %t43 to <3 x fl...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t78: ch = CopyToReg t0, Register:i64 %vreg30, t63
t64: i64 = extract_vector_elt t56, Constant:i64<7>
t80: ch = CopyToReg t0, Register:i64 %vreg31, t64
t81: ch = TokenFactor t66, t68, t70, t72, t74, t76, t78, t80
t83: ch = CopyToReg t0, Register:i64 %vreg209, Constant:i64<0>
t85: ch = TokenFactor t41, t81, t83
t86: ch = br t85, BasicBlock:ch<vector.body25 0x1bd35f0>
I am curious what is wrong - I've tried to match the Mips' back end: I have put most
of the vect...
2017 Feb 28
2
rL296252 Made large integer operation codegen significantly worse.
I see we're missing an isel pattern for add producing carry and doing a
memory RMW. I'm going to see if adding that helps anything.
~Craig
On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Yes. I'm seeing that as well. Not clear what's going on.
>
> In any case it looks to be unrelated to the alias analysis so barring