Displaying 3 results from an estimated 3 matches for "t74".
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2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...float>* %t66, align 16
%t69 = shufflevector <4 x float> %t50, <4 x float> undef, <4 x i32>
zeroinitializer
%t71 = fmul <4 x float> %t55, %t69
%t72 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32>
<i32 1, i32 1, i32 1, i32 1>
%t74 = fmul <4 x float> %t59, %t72
%t75 = fadd <4 x float> %t71, %t74
%t76 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32>
<i32 2, i32 2, i32 2, i32 2>
%t78 = fmul <4 x float> %t63, %t76
%t79 = fadd <4 x float> %t75, %t78
%t80 = sh...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t70: ch = CopyToReg t0, Register:i64 %vreg26, t59
t60: i64 = extract_vector_elt t56, Constant:i64<3>
t72: ch = CopyToReg t0, Register:i64 %vreg27, t60
t61: i64 = extract_vector_elt t56, Constant:i64<4>
t74: ch = CopyToReg t0, Register:i64 %vreg28, t61
t62: i64 = extract_vector_elt t56, Constant:i64<5>
t76: ch = CopyToReg t0, Register:i64 %vreg29, t62
t63: i64 = extract_vector_elt t56, Constant:i64<6>
t78: ch = CopyToR...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...nstant:i64<80>
t71: ch = store<ST16[<unknown>](align=8)> t50, t69, t70, undef:i64
t72: ch = TokenFactor t55:1, t56, t57:1, t59, t60:1, t62, t63:1, t65, t66:1, t68, t69:1, t71
t73: ch,glue = callseq_start t72, TargetConstant:i64<128>, TargetConstant:i64<0>
t74: i64,ch = load<LD8[FixedStack1]> t73, FrameIndex:i64<1>, undef:i64
t76: i64 = add FrameIndex:i64<1>, Constant:i64<8>
t77: i64,ch = load<LD8[FixedStack1+8]> t73, t76, undef:i64
t78: i64,ch = load<LD8[FixedStack1+16]> t73, t27, undef:i64
t80: i64 = add...