search for: t72

Displaying 5 results from an estimated 5 matches for "t72".

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2018 Jun 20
2
Node deletion during DAG Combination ?
...ally smaller) set of DAG nodes, removing dead nodes and updating all the chains'. I'm using the setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT) and build the new LOAD_VECTOR_EXTRACT node in the PerformDAGCombine(). As per the following trace this work, t59 and params from t58 are merged into t72. During this combination, the chain from t59 to t58 has been merged from new t72 to t57, skipping over t58. So far, so good. My problem is that this node t58 is not removed from DAG. One reason could be that node t62 is still chained to t58 (due to the fact the extract_vector_elt has no chain). (I...
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...align 16 %t66 = getelementptr <4 x float>, <4 x float>* %t24, i64 3 %t67 = load <4 x float>, <4 x float>* %t66, align 16 %t69 = shufflevector <4 x float> %t50, <4 x float> undef, <4 x i32> zeroinitializer %t71 = fmul <4 x float> %t55, %t69 %t72 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %t74 = fmul <4 x float> %t59, %t72 %t75 = fadd <4 x float> %t71, %t74 %t76 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32> <i32 2...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t68: ch = CopyToReg t0, Register:i64 %vreg25, t58 t59: i64 = extract_vector_elt t56, Constant:i64<2> t70: ch = CopyToReg t0, Register:i64 %vreg26, t59 t60: i64 = extract_vector_elt t56, Constant:i64<3> t72: ch = CopyToReg t0, Register:i64 %vreg27, t60 t61: i64 = extract_vector_elt t56, Constant:i64<4> t74: ch = CopyToReg t0, Register:i64 %vreg28, t61 t62: i64 = extract_vector_elt t56, Constant:i64<5> t76: ch = CopyToR...
2017 Feb 28
2
rL296252 Made large integer operation codegen significantly worse.
I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...50, t63, t64, undef:i64 t67: i64 = add t10, Constant:i64<64> t68: ch = store<ST16[<unknown>](align=8)> t50, t66, t67, undef:i64 t70: i64 = add t10, Constant:i64<80> t71: ch = store<ST16[<unknown>](align=8)> t50, t69, t70, undef:i64 t72: ch = TokenFactor t55:1, t56, t57:1, t59, t60:1, t62, t63:1, t65, t66:1, t68, t69:1, t71 t73: ch,glue = callseq_start t72, TargetConstant:i64<128>, TargetConstant:i64<0> t74: i64,ch = load<LD8[FixedStack1]> t73, FrameIndex:i64<1>, undef:i64 t76: i64 = add FrameIndex:...