Displaying 7 results from an estimated 7 matches for "t63".
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63
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...i32 6, i32 3>
%t55 = load <4 x float>, <4 x float>* %t24, align 16
%t58 = getelementptr <4 x float>, <4 x float>* %t24, i64 1
%t59 = load <4 x float>, <4 x float>* %t58, align 16
%t62 = getelementptr <4 x float>, <4 x float>* %t24, i64 2
%t63 = load <4 x float>, <4 x float>* %t62, align 16
%t66 = getelementptr <4 x float>, <4 x float>* %t24, i64 3
%t67 = load <4 x float>, <4 x float>* %t66, align 16
%t69 = shufflevector <4 x float> %t50, <4 x float> undef, <4 x i32>
zeroinitial...
2017 Sep 21
1
VSelect Instruction Error
...= load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
t8: i64 = add t7, Constant:i64<4>
t7: i64 = add t2, t63
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg97
t1: i64 = Register %vreg97
t63: i64 = shl t4, Constant:i8<2>
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg11
t3: i64 = Register %vreg11
t1889: i8 = Constant<2>
t5: i64 = C...
2017 Aug 06
2
VBROADCAST Implementation Issues
...;>>>>
>>>>>>>>>>>>> I did as you said;
>>>>>>>>>>>>> now getting this error:
>>>>>>>>>>>>>
>>>>>>>>>>>>> LLVM ERROR: Cannot select: t63: v64f32 = X86ISD::VBROADCAST t62
>>>>>>>>>>>>> t62: f32,ch = load<LD4[ConstantPool]> t0, t65, undef:i64
>>>>>>>>>>>>> t65: i64 = X86ISD::Wrapper TargetConstantPool:i64<float
>>>>>>>>...
2017 Aug 07
2
VBROADCAST Implementation Issues
...t;>>>>>>>>>>> I did as you said;
>>>>>>>>>>>>>>> now getting this error:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> LLVM ERROR: Cannot select: t63: v64f32 = X86ISD::VBROADCAST
>>>>>>>>>>>>>>> t62
>>>>>>>>>>>>>>> t62: f32,ch = load<LD4[ConstantPool]> t0, t65, undef:i64
>>>>>>>>>>>>>>> t65: i64 = X86...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t61: i64 = extract_vector_elt t56, Constant:i64<4>
t74: ch = CopyToReg t0, Register:i64 %vreg28, t61
t62: i64 = extract_vector_elt t56, Constant:i64<5>
t76: ch = CopyToReg t0, Register:i64 %vreg29, t62
t63: i64 = extract_vector_elt t56, Constant:i64<6>
t78: ch = CopyToReg t0, Register:i64 %vreg30, t63
t64: i64 = extract_vector_elt t56, Constant:i64<7>
t80: ch = CopyToReg t0, Register:i64 %vreg31, t64
t81: ch = TokenFactor...
2017 Aug 07
3
VBROADCAST Implementation Issues
...did as you said;
>>>>>>>>>>>>>>>>>>> now getting this error:
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> LLVM ERROR: Cannot select: t63: v64f32 =
>>>>>>>>>>>>>>>>>>> X86ISD::VBROADCAST t62
>>>>>>>>>>>>>>>>>>> t62: f32,ch = load<LD4[ConstantPool]> t0, t65,
>>>>>>>>>>>>>>&...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...lt;0>
t54: i32 = Constant<96>
t55: v4i32,ch = load<LD16[FixedStack1](align=8)> t50, FrameIndex:i64<1>, undef:i64
t57: v4i32,ch = load<LD16[FixedStack1+16](align=8)> t50, t27, undef:i64
t60: v4i32,ch = load<LD16[FixedStack1+32](align=8)> t50, t31, undef:i64
t63: v4i32,ch = load<LD16[FixedStack1+48](align=8)> t50, t36, undef:i64
t66: v4i32,ch = load<LD16[FixedStack1+64](align=8)> t50, t41, undef:i64
t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64
t56: ch = store<ST16[<unknown>](align=8)> t50,...