search for: t58

Displaying 4 results from an estimated 4 matches for "t58".

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2018 Jun 20
2
Node deletion during DAG Combination ?
...DAG nodes by an (usually smaller) set of DAG nodes, removing dead nodes and updating all the chains'. I'm using the setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT) and build the new LOAD_VECTOR_EXTRACT node in the PerformDAGCombine(). As per the following trace this work, t59 and params from t58 are merged into t72. During this combination, the chain from t59 to t58 has been merged from new t72 to t57, skipping over t58. So far, so good. My problem is that this node t58 is not removed from DAG. One reason could be that node t62 is still chained to t58 (due to the fact the extract_vector_e...
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...ctor <4 x float> %t48, <4 x float> %t46, <4 x i32> <i32 0, i32 5, i32 undef, i32 3> %t50 = shufflevector <4 x float> %t49, <4 x float> %t47, <4 x i32> <i32 0, i32 1, i32 6, i32 3> %t55 = load <4 x float>, <4 x float>* %t24, align 16 %t58 = getelementptr <4 x float>, <4 x float>* %t24, i64 1 %t59 = load <4 x float>, <4 x float>* %t58, align 16 %t62 = getelementptr <4 x float>, <4 x float>* %t24, i64 2 %t63 = load <4 x float>, <4 x float>* %t62, align 16 %t66 = getelementptr &lt...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t40: ch = CopyToReg t0, Register:i64 %vreg23, t24 t41: ch = TokenFactor t26, t28, t30, t32, t34, t36, t38, t40 t57: i64 = extract_vector_elt t56, Constant:i64<0> t66: ch = CopyToReg t0, Register:i64 %vreg24, t57 t58: i64 = extract_vector_elt t56, Constant:i64<1> t68: ch = CopyToReg t0, Register:i64 %vreg25, t58 t59: i64 = extract_vector_elt t56, Constant:i64<2> t70: ch = CopyToReg t0, Register:i64 %vreg26, t59 t60: i64 = extrac...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...xedStack1+48](align=8)> t50, t36, undef:i64 t66: v4i32,ch = load<LD16[FixedStack1+64](align=8)> t50, t41, undef:i64 t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64 t56: ch = store<ST16[<unknown>](align=8)> t50, t55, t10, undef:i64 t58: i64 = add t10, Constant:i64<16> t59: ch = store<ST16[<unknown>](align=8)> t50, t57, t58, undef:i64 t61: i64 = add t10, Constant:i64<32> t62: ch = store<ST16[<unknown>](align=8)> t50, t60, t61, undef:i64 t64: i64 = add t10, Constant:i6...