search for: t50

Displaying 13 results from an estimated 13 matches for "t50".

Did you mean: 50
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...ave a patch posted implementing 2, but don't know if I should look at fixing 1 as well (or perhaps instead). The loads that trigger the assertion are: t47: v4i32,ch = load<LD16[%0+80](align=8)(dereferenceable)> t20, t46, undef:i64 t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64 I would expect the the second load should also be marked dereferenceable since its loading from one of the TargetFrames. Am I on the right track here? Thanks Sean -------------- next part -------------- Initial selection DAG: BB#0 '_Z3fn2v:entry' SelectionDAG has 122 nodes...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t46: ch,glue = callseq_start t0, TargetConstant:i32<0> t47: ch,glue = CopyToReg t46, Register:i64 %reg0, t2 t48: ch,glue = CopyToReg t47, Register:i64 %reg1, t4, t47:1 t50: ch,glue = SHAVEISD::CALL t48, TargetExternalSymbol:i32'__divdi3', Register:i64 %reg0, Register:i64 %reg1, RegisterMask:Untyped, t48:1 t51: ch,glue = callseq_end t50, TargetConstant:i32<0>, TargetExternalSymbol:i32'__divdi3', t50:1 t52: i64,ch,glue = CopyFromReg t51, Regis...
2018 May 04
0
How to constraint instructions reordering from patterns?
...lt;0x3dbe418>)> t8, ConstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 ... into: t51: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, Constant:i32<1065353216>, GlobalAddress:i16<float* @x1> 0, undef:i16 An a new Constant:i32 node (t50) is created. The question is: Where in the graph is created this node? This node seems to be created before the EntryToken !!! Before the initialization of my Stack Pointer registers (RSPA,RSPB,RSPSU). Why isn't it created between t8 and t51? t0: ch = EntryToken...
2009 Feb 15
2
cannot read words on any wine screen
...to even configure it due to a lack of text on the configure screen. when i change tabs there is a sudden flash of jumbled texts that immediately subsides. and i am using nvdia drivers for my graphics card. here is what it looks like (title bar got cut off) [Image: http://i157.photobucket.com/albums/t50/anbu-naru/bokwe.jpg ]
2018 May 04
2
How to constraint instructions reordering from patterns?
...onstantFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, undef:i16 > > ... into: t51: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > Constant:i32<1065353216>, GlobalAddress:i16<float* @x1> 0, undef:i16 > > An a new Constant:i32 node (t50) is created. > > /The question is: Where in the graph is created this node?/ > > This node seems to be created before the EntryToken !!! Before the > initialization of my Stack Pointer registers (RSPA,RSPB,RSPSU). > > Why isn’t it created between t8 and t51? > > t0:...
2018 May 04
2
How to constraint instructions reordering from patterns?
Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into
2018 May 04
0
How to constraint instructions reordering from patterns?
...tFP:f32<1.000000e+00>, GlobalAddress:i16<float* @x1> 0, > undef:i16 > > ... into: t51: ch = store<Volatile ST4[@x1](tbaa=<0x3dbe418>)> t8, > Constant:i32<1065353216>, GlobalAddress:i16<float* @x1> 0, undef:i16 > > An a new Constant:i32 node (t50) is created. > > /The question is: Where in the graph is created this node?/ > > This node seems to be created before the EntryToken !!! Before the > initialization of my Stack Pointer registers (RSPA,RSPB,RSPSU). > > Why isn’t it created between t8 and t51? > > t0:...
2008 Mar 07
1
Finding Interaction and main effects contrasts for two-way ANOVA
I've tried without success to calculate interaction and main effects contrasts using R. I've found the functions C(), contrasts(), se.contrasts() and fit.contrasts() in package gmodels. Given the url for a small dataset and the two-way anova model below, I'd like to reproduce the results from appended SAS code. Thanks. --Dale. ## the dataset (from Montgomery) twoway <-
2011 Nov 11
1
Predicting x from y
Dear list members, I have just a quick question: I fitted a non-linear model y=a/x+b to describe my data (x=temperature and y=damage in %) and it works really nicely (see example below). I have 7 different species and 8 individuals per species. I measured damage for each individual per species at 4 different temperatures (e.g. -5, -10, -20, -40). Using the individuals per species, I fitted one
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
...gt; %t44, <3 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 2, i32 undef> %t48 = insertelement <4 x float> %t45, float 1.000000e+00, i32 3 %t49 = shufflevector <4 x float> %t48, <4 x float> %t46, <4 x i32> <i32 0, i32 5, i32 undef, i32 3> %t50 = shufflevector <4 x float> %t49, <4 x float> %t47, <4 x i32> <i32 0, i32 1, i32 6, i32 3> %t55 = load <4 x float>, <4 x float>* %t24, align 16 %t58 = getelementptr <4 x float>, <4 x float>* %t24, i64 1 %t59 = load <4 x float>, <4 x flo...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...Continuing at 396 Match failed at index 398 Continuing at 422 LLVM ERROR: Cannot select: t51: v8i64,ch = load<LD64[ConstantPool]> t0, ConstantPool:i64<<8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>> 0, undef:i64 t50: i64 = ConstantPool<<8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>> 0 t48: i64 = undef In function: foo The reason is that for the basic-block my back end generates the following Selection DAG: (From 201_LoopVectorize/25_GOOD...
2008 Mar 26
3
HW experience
Hi, we would like to establish a small Lustre instance and for the OST planning to use standard Dell PE1950 servers (2x QuadCore + 16 GB Ram) and for the disk a JBOD (MD1000) steered by the PE1950 internal Raid controller (Raid-6). Any experience (good or bad) with such a config ? thanxs, Martin
2003 Feb 27
3
Intercom and Paging
What models? Jeff Noxon (jeff-asterisk at planetfall.com) wrote*: > >I just purchased a bunch of Nortel Meridian POTS phones that support >intercom on the 3rd pair. I intend to get it working with Asterisk. >The phones support MWI, have a 3-line display, callerID, call waiting >callerID, 2 lines...very nice. > >On Thu, Feb 27, 2003 at 01:07:19AM -1000, James H. Thompson