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...2 at 1104r merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B erased:464r%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47 AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X %T14_Y %T14_Z %T14_W %T15_X %T15_Y %T15_Z %T15_W %T16_X %T16...

...5:0 at 464r into %vreg47:1 at 448B --> @448B > erased:464r%vreg5<def> = COPY %vreg47<kill>; > R600_Reg32:%vreg5,%vreg47 > AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W > %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X > %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y > %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y > %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X > %T14_Y %T14_Z %T14_W %T15_X %T15_Y %...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2