Displaying 4 results from an estimated 4 matches for "t3_x".
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t1_x
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
..._X, %T2_XYZW<imp-def>
192B%T2_Y<def> = COPY %C1_Y, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
272B%T2_Z<def> = COPY %C1_Z, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
320B%T2_W<def> = COPY %C1_W, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
368B%T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0
Successors according to CFG: BB#1
448BBB#1: derived from LLVM BB %25
Live Ins: %T1_XYZW %T2_XYZW %T3_X
Predecessors according to CFG: BB#0 BB#3
512B%T3_Y<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0,...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...def>
> 192B%T2_Y<def> = COPY %C1_Y, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
> 272B%T2_Z<def> = COPY %C1_Z, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
> 320B%T2_W<def> = COPY %C1_W, %T2_XYZW<imp-use,kill>, %T2_XYZW<imp-def>
> 368B%T3_X<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0
> Successors according to CFG: BB#1
>
> 448BBB#1: derived from LLVM BB %25
> Live Ins: %T1_XYZW %T2_XYZW %T3_X
> Predecessors according to CFG: BB#0 BB#3
> 512B%T3_Y<def> = SETGT_IN...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...)[1104r,1168B:2) 0 at 400r 1 at 448B-phi 2 at 1104r
merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
erased:464r%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X %T14_Y %T14_Z %T14...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...448B-phi
> 2 at 1104r
> merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B
> erased:464r%vreg5<def> = COPY %vreg47<kill>;
> R600_Reg32:%vreg5,%vreg47
> AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W
> %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X
> %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y
> %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y
> %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W %T13_X %T13_Y %T13_Z %T13_W %T14_X...