search for: t39

...ALLEE_A t29, t23, FrameIndex:i16<0>, t29:1 t33: ch,glue = CLPISD::COPY_TO_CALLEE_A t31, t24, FrameIndex:i16<1>, t31:1 t35: ch,glue = CLPISD::COPY_TO_CALLEE_A t33, t25, FrameIndex:i16<2>, t33:1 t37: ch,glue = CLPISD::COPY_TO_CALLEE_A t35, t26, FrameIndex:i16<3>, t35:1 t39: ch,glue = CLPISD::CALLSEQ t37, TargetGlobalAddress:i16<float (float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, TargetConstant:i16<0>, t39:1 t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t41, FrameIndex:i16<0>,...

...: ch,glue = CLPISD::COPY_TO_CALLEE_A t31, t24, FrameIndex:i16<1>, > t31:1 > >   t35: ch,glue = CLPISD::COPY_TO_CALLEE_A t33, t25, FrameIndex:i16<2>, > t33:1 > >   t37: ch,glue = CLPISD::COPY_TO_CALLEE_A t35, t26, FrameIndex:i16<3>, > t35:1 > >   t39: ch,glue = CLPISD::CALLSEQ t37, TargetGlobalAddress:i16<float > (float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 > > t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, > TargetConstant:i16<0>, t39:1 > > t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...ISD::COPY_TO_CALLEE_A t31, t24, > FrameIndex:i16<1>, > t31:1 > >   t35: ch,glue = CLPISD::COPY_TO_CALLEE_A t33, t25, > FrameIndex:i16<2>, > t33:1 > >   t37: ch,glue = CLPISD::COPY_TO_CALLEE_A t35, t26, > FrameIndex:i16<3>, > t35:1 > >   t39: ch,glue = CLPISD::CALLSEQ t37, TargetGlobalAddress:i16<float > (float, float, float, float)* @fdivfaddfmul_a> 0, t37:1 > > t41: ch,glue = callseq_end t39, TargetConstant:i16<4>, > TargetConstant:i16<0>, t39:1 > > t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t...

...dolore magna aliquam erat #volutpat. "??????????????????????????????????? ?#[2] "Ut wisi enim ad minim veniam, quis nostrud exerci tation ullamcorper suscipit #lobortis"?????????????????????????????????????????????????????????????????????????????????????????????? # [3] "38\t43\t39\t44\t45"?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? ?#[4] "39\t44\t36\t49\t46"??????????????????????????????????????????????????????????????????????????????????????...

...stant:i64<-4>, Constant:i64<-5>, Constant:i64<-6>, Constant:i64<-7> t33: v8i64 = add t24, t32 t35: ch = CopyToReg t0, Register:v8i64 %vreg17, t33 t37: ch = CopyToReg t0, Register:i64 %vreg117, Constant:i64<0> t39: ch = TokenFactor t18, t35, t37 t40: ch = br t39, BasicBlock:ch<vector.body25 0x1d07660> However, when using the mips64 back end (subtarget) we get this correct selection DAG: (From 201_LoopVectorize/25_GOOD_map/NEW/6/1/NEW/Mips64/STDerr_llc_mips64) Initial...

I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring

...0>, Constant:i64<16> t30: ch = store<ST16[%1+16]> t20, t28, t29, undef:i64 t33: i64 = add FrameIndex:i64<0>, Constant:i64<32> t34: ch = store<ST16[%1+32]> t20, t32, t33, undef:i64 t38: i64 = add FrameIndex:i64<0>, Constant:i64<48> t39: ch = store<ST16[%1+48]> t20, t37, t38, undef:i64 t43: i64 = add FrameIndex:i64<0>, Constant:i64<64> t44: ch = store<ST16[%1+64]> t20, t42, t43, undef:i64 t48: i64 = add FrameIndex:i64<0>, Constant:i64<80> t49: ch = store<ST16[%1+80]> t2...

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

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