Displaying 4 results from an estimated 4 matches for "t34".
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34
2017 Feb 28
2
rL296252 Made large integer operation codegen significantly worse.
I see we're missing an isel pattern for add producing carry and doing a
memory RMW. I'm going to see if adding that helps anything.
~Craig
On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Yes. I'm seeing that as well. Not clear what's going on.
>
> In any case it looks to be unrelated to the alias analysis so barring
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t30: ch = CopyToReg t0, Register:i64 %vreg18, t19
t20: i64 = extract_vector_elt t16, Constant:i64<3>
t32: ch = CopyToReg t0, Register:i64 %vreg19, t20
t21: i64 = extract_vector_elt t16, Constant:i64<4>
t34: ch = CopyToReg t0, Register:i64 %vreg20, t21
t22: i64 = extract_vector_elt t16, Constant:i64<5>
t36: ch = CopyToReg t0, Register:i64 %vreg21, t22
t23: i64 = extract_vector_elt t16, Constant:i64<6>
t38: ch = CopyToR...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...6, undef:i64
t25: ch = store<ST16[%1]> t20, t24, FrameIndex:i64<0>, undef:i64
t29: i64 = add FrameIndex:i64<0>, Constant:i64<16>
t30: ch = store<ST16[%1+16]> t20, t28, t29, undef:i64
t33: i64 = add FrameIndex:i64<0>, Constant:i64<32>
t34: ch = store<ST16[%1+32]> t20, t32, t33, undef:i64
t38: i64 = add FrameIndex:i64<0>, Constant:i64<48>
t39: ch = store<ST16[%1+48]> t20, t37, t38, undef:i64
t43: i64 = add FrameIndex:i64<0>, Constant:i64<64>
t44: ch = store<ST16[%1+64]> t2...
2019 Jul 11
6
Glue to connect two nodes in LLVM backend
Hello everyone,
I wanted to attach a node without affecting the present nodes in any way. I
tried to use MVT::Glue for that but I think I'm missing something as I
could not achieve the below state.
LUI LUI
| |
ADDI ----GLUE---- ADDI
|
store
I've few question about this and Glue node in general, I'll be happy to get
some help on