search for: t32

Displaying 20 results from an estimated 22 matches for "t32".

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2016 Jun 25
2
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All, I have a problem with VectorLegalizer::ExpandStore() with v4i1. Let's see a example. * LLVM IR store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27 * SelectionDAG before vector legalization ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64 * SelectionDAG after vector legalization ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64 t133: i32 = extract_vector_elt t128, Constant:i64<0> ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32, undef:i64 t136: i32 = extract_vector_elt t128...
2016 Jun 28
0
Question about VectorLegalizer::ExpandStore() with v4i1
...a problem with VectorLegalizer::ExpandStore() with v4i1. > > Let's see a example. > > * LLVM IR > store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27 > > * SelectionDAG before vector legalization > ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64 > > * SelectionDAG after vector legalization > ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64 > t133: i32 = extract_vector_elt t128, Constant:i64<0> > ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32, undef:i64 > t136:...
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
...ExpandStore() with v4i1. >> >> Let's see a example. >> >> * LLVM IR >> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27 >> >> * SelectionDAG before vector legalization >> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64 >> >> * SelectionDAG after vector legalization >> ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32, undef:i64 >> t133: i32 = extract_vector_elt t128, Constant:i64<0> >> ch = store<ST1[%16](align=4), trunc to i1> t0, t136, t32, und...
2016 May 18
2
LLVM issuse:AArch64 TargetParser
Hi, A64 versus A32/T32 code generation is controlled by the -target option which I don’t believe is under discussion here. James On 18 May 2016, at 13:17, Bruce Hoult <bruce at hoult.org<mailto:bruce at hoult.org>> wrote: Note that armv8a modifies the A32 and T32 instruction sets, and is therefore an import...
2016 May 05
4
LLVM issuse:AArch64 TargetParser
Hi everyone, I'm a member engineer of linaro's llvm team,coming from Spreadtrum.I am a new person on LLVM.Now I'm writing a Target Parser for AArch64,so options parsing of AArch64 about cpu & arch & fpu can be summary to one place. In the TargetParser,we assume "aarch64" and "arm64" are synonyms of armv8a(as they are only for armv8a,people usually do
2019 Dec 09
2
[PATCH] D70246: [InstCombine] remove identity shuffle simplification for mask with undefs
Sanjay, I'm looking at some missed optimizations caused by D70246. Here's a test case: define <4 x float> @f(i32 %t32, <4 x float>* %t24) { .entry: %t43 = insertelement <3 x i32> undef, i32 %t32, i32 2 %t44 = bitcast <3 x i32> %t43 to <3 x float> %t45 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %t46...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64 t32: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<-1>, Constant:i64<-2>, Constant:i64<-3>, Constant:i64<-4>, Constant:i64<-5>, Constant:i64<-6>, Constant:i64<-7> t33: v8i64 = add t24, t32 t35: ch = CopyToReg t0, Reg...
2019 Aug 27
2
TargetRegisterInfo::getCommonSubClass bug, perhaps.
...1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; ===== Instruction selection ends: ... t8: i32 = ADDrr t37, t32 ... Instruction Selection correct : i32 = ADDrr i32, i32 *** MachineFunction at end of ISel *** # Machine code for function _Z11scalar_loopPsS_ss: IsSSA, TracksLiveness ... %31:sfgpr32 = ADDrr killed %32:sgpr32, %27:sgpr32 ... Here should not select f32 sfgpr32 register, debugger point to Targe...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...;LD16[%0](align=8)(dereferenceable)> t20, FrameIndex:i64<1>, undef:i64 t27: i64 = add FrameIndex:i64<1>, Constant:i64<16> t28: v4i32,ch = load<LD16[%0+16](align=8)(dereferenceable)> t20, t27, undef:i64 t31: i64 = add FrameIndex:i64<1>, Constant:i64<32> t32: v4i32,ch = load<LD16[%0+32](align=8)(dereferenceable)> t20, t31, undef:i64 t36: i64 = add FrameIndex:i64<1>, Constant:i64<48> t37: v4i32,ch = load<LD16[%0+48](align=8)(dereferenceable)> t20, t36, undef:i64 t41: i64 = add FrameIndex:i64<1>, Constant:i64<64>...
2017 Feb 11
2
Specify special cases of delay slots in the back end
Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the
2018 Nov 15
2
[RFC][ARM] -Oz implies -mthumb
...-mcpu=cortex-xyz does not really give minimum code size because -mthumb is not enabled. This looks like a sub-optimal user experience to me, and also, it is inconsistent with GCC's behaviour. In other words: for AArch32, optimisation level -Oz targets A32, but I would like to change that to T32, and so I would like to propose that -Oz implies -mthumb. Cheers, Sjoerd. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to...
2019 Jun 02
2
Optimizing Compare instruction selection
...Apparently, LLVM attempts to physically use the result of a CMP instruction through a function call by storing it on a temporary register. This is found before the doSmth function call, t30: i16 = CMPkr16 t4, TargetConstant:i16<0> t36: ch,glue = CopyToReg t0, Register:i16 $sr, t30 t32: i16 = NEGSETCC TargetConstant:i16<4>, t36:1 And this is generated after the call t35: ch,glue = CopyToReg t0, Register:i16 $sr, t30 t31: i16 = SELCC t19, t18, TargetConstant:i16<4>, t35:1 t21: ch,glue = CopyToReg t18:1, Register:i16 $r0, t31 NEGSETCC and SELCC are genui...
2018 Jul 02
2
Rotates, once again
...ful generalization of a vector funnel shift in this context is lane-wise    result[i] = trunc(concat(a[i], b[i]) >> c[i]) (or the equivalent for a left shift); the special case a==b is a rotate. 2. For operand sizes that have native rotate instructions, at least x86, x86-64, ARM A32/T32 and AArch64 A64 agree that rotate distances are modulo the operand width. I believe PPC and MIPS do the same but am not sure (it's been a while), no clue about other architectures. It certainly seems the most natural way to define it, since rotates are cyclic to begin with. 8- and 16-bit r...
2019 Jun 05
2
Optimizing Compare instruction selection
...tempts to physically use the result of a CMP instruction through a function call by storing it on a temporary register. This is found before the doSmth function call, > > t30: i16 = CMPkr16 t4, TargetConstant:i16<0> > t36: ch,glue = CopyToReg t0, Register:i16 $sr, t30 > t32: i16 = NEGSETCC TargetConstant:i16<4>, t36:1 > > > And this is generated after the call > > t35: ch,glue = CopyToReg t0, Register:i16 $sr, t30 > t31: i16 = SELCC t19, t18, TargetConstant:i16<4>, t35:1 > t21: ch,glue = CopyToReg t18:1, Register:i16 $r...
2004 Aug 07
2
segmentation error
...4096) = 4096 write(6, "CHARSET\"=\"ISO-8859-1\"\n\"EREG\"=\"C:"..., 4096) = 4096 write(6, "Installer Package\"\n\n[Software\\\\Z"..., 4096) = 4096 write(6, "DLL\"\n\n[Software\\\\ODBC\\\\ODBCINST."..., 4096) = 4096 write(6, "t32.dll\"\n\"Setup\"=\"C:\\\\WINDOWS\\\\S"..., 4096) = 4096 write(6, "isc\"=dword:00000001\n\"CacheDiskOr"..., 4096) = 4096 write(6, "rategy\"=dword:00000003\n\"MaxFileS"..., 4096) = 4096 write(6, "] CDTSD[6] NEROCD95[8] BsUDF[10]&qu...
2020 Jul 05
8
[RFC] carry-less multiplication instruction
<div> </div><div><div><p>Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious,
2018 May 17
3
Rotates, once again
Thanks Sanjay! At this point the cost/benefit tradeoff for rotate intrinsics seems pretty good. John On 05/17/2018 11:14 AM, Sanjay Patel wrote: > A rotate intrinsic should be relatively close in cost/complexity to the > existing bswap. > > A grep of intrinsic::bswap says we'd probably add code in: > InstCombine > InstructionSimplify >
2019 Jun 01
2
Optimizing Compare instruction selection
I attempt to optimize the use of the ‘CMP’ instruction on my architecture by removing the instruction instances where the Status Register already had the correct status flags. The cmp instruction in my architecture is the typical one that compares two registers, or a register with an immediate, and sets the Status Flags accordingly. I implemented my ‘cmp’ instruction in LLVM by custom lowering
2014 Dec 02
4
T.38 not working - help needed with log interpretation
Dear all, I have the following situation: Local T.38 endpoint <-> ASTERISK <-> SIP provider (with T.38 support) I am trying to send a fax from my local T.38 endpoint to arbitrary external fax numbers (which I am not in control of, so I don't know if the other end supports T.38, is connected to a PBX, who is their provider, and so on), of course trying to use T.38 at least from
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
...MCFragment *DF, + MCValue &Target, uint64_t &Value, + bool &IsResolved) { + AArch64AsmBackend::processFixupValue(Asm, Layout, Fixup, DF, Target, Value, + IsResolved); + if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_call) + IsResolved = false; + } + void relaxInstruction(const MCInst &, llvm::MCInst &) const { + llvm_unreachable("Cannot relax instructions"); + } + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + con...