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t2ldrhi12
2013 May 13
0
[LLVMdev] [ARM] Bugs in decode / encode of PC-relative t2 LDR in the ARM backend
...esn't seem to trigger this issue, because either the correct variant is always selected, or certain combinations of parameters never occur, I haven't been looking into that heavily yet.
The basic issue is that an instruction such as LDR.W r0, [pc, #1] (positive immediate) will decode into t2LDRi12, whereas the same literal load with a negative immediate will randomly either fail to decode (test with 0x5f 0xf8 0x01 0x20 which should bd LDR.W r2, [pc, #-1]), or decode to some predictable version of t2LDRT, t2LDRi8, etc... based on certain bits in the immediate matching the ones set in the c...