Displaying 3 results from an estimated 3 matches for "t2i_ld".
2013 May 13
0
[LLVMdev] [ARM] Bugs in decode / encode of PC-relative t2 LDR in the ARM backend
I've been working with the ARM backend's disassembler and working it out pretty heavily over the past several months, and have run into a bug involving the LDR instruction and all variants which use the T2I_ld multiclass. Codegen doesn't seem to trigger this issue, because either the correct variant is always selected, or certain combinations of parameters never occur, I haven't been looking into that heavily yet.
The basic issue is that an instruction such as LDR.W r0, [pc, #1] (positive imm...
2012 Feb 17
0
[LLVMdev] ARM/Thumb2/ISEL Need help tracing down a failing match: (HOW?)
...I suppose there are several things that could be broken:
1. There is a bug in the patterns I specified in the .td file
2. There is some hardcoded glue in ARMInstrThumb2.td that prevents the
expected match from happening (perhaps something to do with 'pci' pattern
in multiclass T2I_ld ??)
3. There is some other glue that prevents the pattern from matching
(perhaps in ARMISelLowering - which *does* have custom code..)
Assuming that the case is the first or second, what is the best way to
associate the table information in ARMGenDAGISel.inc to the entries in the
.td file? T...
2013 May 23
3
[LLVMdev] Definition of RegisterClass for load instruction in Thumb2
...t the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8:$addr),...