search for: t24

Sanjay, I'm looking at some missed optimizations caused by D70246. Here's a test case: define <4 x float> @f(i32 %t32, <4 x float>* %t24) { .entry: %t43 = insertelement <3 x i32> undef, i32 %t32, i32 2 %t44 = bitcast <3 x i32> %t43 to <3 x float> %t45 = shufflevector <3 x float> %t44, <3 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %t46 = shufflevector <3 x f...

Dear all, I am trying to estimate the marginal effects of a logit regression using the mfx package. It is crucial that the standard errors are clustered at the year level. Hence, the code looks as follows: marginal.t24.2<-logitmfx(stock.market.crash~crash.t24+bubble.t24+RV.t24,data=Data_logitregression_lags, clustervar1 = "year") marginal.t24.4<-logitmfx(stock.market.crash~crash.t24+bubble.t24+MP.t24+UTS.t24+UPR.t24+PPI.t24+RV.t24,data=Data_logitregression_lags, clustervar1 = "year")...

...ta Grouped Data: lnCount ~ Time | Type Time Mouse Count Type lnCount 1 0 T0-1 37.6 Naive 3.627004 2 0 T0-2 23.6 Naive 3.161247 3 0 T0-3 49.2 Naive 3.895894 4 8 T8-1 20.8 Naive 3.034953 5 8 T8-2 26.9 Naive 3.292126 6 8 T8-3 34.0 Naive 3.526361 7 24 T24-1 36.8 Naive 3.605498 8 24 T24-2 34.0 Naive 3.526361 9 24 T24-3 19.6 Naive 2.975530 10 48 T48-1 55.4 Naive 4.014580 11 48 T48-2 54.2 Naive 3.992681 12 48 T48-3 51.4 Naive 3.939638 13 0 T0-1 342.0 Memory 5.834811 14 0 T0-2 139.0 Memory 4.934474 15 0 T0-3 191.0 Mem...

...; 0, undef:i16 t22: ch = store<Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, undef:i16 t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, GlobalAddress:i16<float* @x1> 0, undef:i16 t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, GlobalAddress:i16<float* @x2> 0, undef:i16 t25: f32,ch = load<Volatile LD4[@x3](tbaa=<0x3dbe418>)> t24:1, GlobalAddress:i16<float* @x3> 0, undef:i16 t26: f32,ch = load<Volatile LD4[@x4](tbaa=<0x...

...e<Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, > ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, undef:i16 > > t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, > GlobalAddress:i16<float* @x1> 0, undef:i16 > >   t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, > GlobalAddress:i16<float* @x2> 0, undef:i16 > >   t25: f32,ch = load<Volatile LD4[@x3](tbaa=<0x3dbe418>)> t24:1, > GlobalAddress:i16<float* @x3> 0, undef:i16 > >   t26: f32,ch = l...

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

...m: Items:[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11]/Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t0\t12\t18\t00\t00\t11/Elina 'Konsertissa. En tod. vastaa teille'\tEtu-Töölö, Helsinki (2:40)\t24\t12\t18\t00\t00\t11 I want to parsing the above data into the below according to each "/": [Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11] Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t...

...the variables in a dataframe, called 'T1A' here. Seems renaming was successful, but when I call one of the variable I got error message and I wanted to know why. The data frame contains 365 rows and 49 columns. I would like to name the first column `DATE` and the others T0.5, T1, T1.5,...,T24 (as this is a set of data collected every half hour for a whole year). Original data is saved as csv file and column 2-49 are named in format '00:30,01:00,01:30,...,23:30,00:00'. When I read them into R by using read.csv, the column names are changed automatically as 'X0.30.00, X1.00.0...

...Volatile ST4[@x4](tbaa=<0x3dbe418>)> t19, > ConstantFP:f32<4.000000e+00>, GlobalAddress:i16<float* @x4> 0, > undef:i16 > > t23: f32,ch = load<Volatile LD4[@x1](tbaa=<0x3dbe418>)> t22, > GlobalAddress:i16<float* @x1> 0, undef:i16 > >   t24: f32,ch = load<Volatile LD4[@x2](tbaa=<0x3dbe418>)> t23:1, > GlobalAddress:i16<float* @x2> 0, undef:i16 > >   t25: f32,ch = load<Volatile LD4[@x3](tbaa=<0x3dbe418>)> t24:1, > GlobalAddress:i16<float* @x3> 0, undef:i16 > >   t26: f32,ch = loa...

...g t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt t13, t15 t17: i32 = extract_vector_el...

...ch = CopyToReg t0, Register:v8i64 %vreg16, t16 t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5 t22: i64 = AssertSext t20, ValueType:ch:i8 t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0> t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64 t32: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<-1>, Constant:i64<-2>, Constant:i64<-3>, Constant:i64<-4>, Constant:i64<-5>, Constant:i64<-6>, Constant:i64<-7&gt...

...+or? I think the > answer is 'yes'. We probably should add that fold. This seems like a > similar case as the recent: https://reviews.llvm.org/D48466 > > Note that on x86, the sext+add becomes zext+sub: > t20: i8 = setcc t3, Constant:i16<-1>, setgt:ch > t24: i16 = zero_extend t20 > t17: i16 = sub Constant:i16<5>, t24 > > Would that transform help your target? > > On Tue, Jul 3, 2018 at 3:55 PM, Yuan Lin <yualin at google.com> wrote: > >> Hi, Roman and Sanjay, >> >> Thank you for your reply! We cur...

...eg1 > t7: i32 = AssertZext t5, ValueType:ch:i1 > t8: v2i32 = BUILD_VECTOR t2, t7 > t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> > t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 > t22: i32 = add t15, Constant:i32<1> > t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 > t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> > t31: ch = TokenFactor t24, t27 > t13: v2i1 = setcc t8, t11, setne:ch > t16: i1 = extract_vector_elt t13, t15 > t17: i32...

...g t2:1, Register:i32 %vreg1 t7: i32 = AssertZext t5, ValueType:ch:i1 t8: v2i32 = BUILD_VECTOR t2, t7 t11: v2i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<-23> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2 t22: i32 = add t15, Constant:i32<1> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22 t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1> t31: ch = TokenFactor t24, t27 t13: v2i1 = setcc t8, t11, setne:ch t16: i1 = extract_vector_elt t13, t15 t17: i32 = extract_vector_el...

...ero. You can see this in the debug output from llc: SelectionDAG has 15 nodes: t0: ch = EntryToken t21: i32 = X86ISD::KORTEST t19, t19 t22: i8 = X86ISD::SETCC Constant:i8<4>, t21 t23: i32 = zero_extend t22 t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23 t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from i8> t0, FrameIndex:i64<0>, undef:i64 t26: i16 = AssertZext t24, ValueType:ch:i4 t19: v16i1 = bitcast t26 t15: ch = X86ISD::RET_FLAG t14, TargetConstant:i32<0>, Register:i32 %EAX, t14:1 -Eli -- Employee o...

...g -debug to llc to see what's happening at various stages of DAG optimization: clang -O0 -mllvm -debug -S failing.c -o failing.s The initial selection DAG has the AND op node: t22: i8 = srl t19, Constant:i64<1> * t23: i8 = and t22, Constant:i8<1>* t24: i32 = zero_extend t23 t27: i1 = setcc t24, Constant:i32<1>, seteq:ch t29: i1 = xor t27, Constant:i1<-1> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48> t33: ch = br t31, BasicBlock:ch<if.then 0xa5f8c98> The Optimized lowered selection DAG do...

Number of subjects = 25 Mean of Sample = 77 Standard Deviation (s) = 12 sem = 2.4 df = 24 The claim is that population mean is less than 80 * > 80 So our H0 (null hupotheis) is * > 80 > qt(.95,24) [1] 1.710882 > qt(0.05, 24) [1] -1.710882 tstat = -1.25 on t24 falls between 1.711 (.95,24) and *1.711 (.005,24) How Could I sketch t curve for the above data where my * would be at the center? Best Regards Isaac Dr. I. Barjis Assistant Professor Summer and Evening Coordinator Department of Biological Sciences Room P313 300 Jay Street Brooklyn, NY 11201...

I see we're missing an isel pattern for add producing carry and doing a memory RMW. I'm going to see if adding that helps anything. ~Craig On Mon, Feb 27, 2017 at 8:47 PM, Nirav Davé via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes. I'm seeing that as well. Not clear what's going on. > > In any case it looks to be unrelated to the alias analysis so barring

...at various > stages of DAG optimization: > > clang -O0 -mllvm -debug -S failing.c -o failing.s > > The initial selection DAG has the AND op node: > > t22: i8 = srl t19, Constant:i64<1> > * t23: i8 = and t22, Constant:i8<1>* > t24: i32 = zero_extend t23 > t27: i1 = setcc t24, Constant:i32<1>, seteq:ch > t29: i1 = xor t27, Constant:i1<-1> > t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48> > t33: ch = br t31, BasicBlock:ch<if.then 0xa5f8c98> > > The Optim...

...µm"), c("Focused", "10k", "A12", "t16.tif", "+", "µm"), c("Focused", "10k", "A12", "t20.tif", "+", "µm"), c("Focused", "10k", "A12", "t24.tif", "+", "µm"), c("Focused", "10k", "A12", "t36.tif", "+", "µm"), c("Focused", "10k", "A12", "t48.tif", "+", "µm"), c("Focused", &qu...