Displaying 20 results from an estimated 49 matches for "t20".
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2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...ded to the FoldingSetNodeID.
3) Something else I haven't considered.
I have a patch posted implementing 2, but don't know if I should look
at fixing 1 as well (or perhaps instead). The loads that trigger the
assertion are:
t47: v4i32,ch = load<LD16[%0+80](align=8)(dereferenceable)> t20, t46, undef:i64
t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64
I would expect the the second load should also be marked
dereferenceable since its loading from one of the TargetFrames. Am I
on the right track here?
Thanks
Sean
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2009 Oct 29
1
strsplit() and Windows file paths
There are two ways to express file paths with the Windows environment:
> a=file.choose()
> a
[1] "C:\\Documents and Settings\\rbaer\\Desktop\\_VNT_Test\\coordFocused 20k F5 0ng Ki8751 t20.txt"
and
>b= paste(getwd(),"/",dir()[1],sep="")
>b
[1] "C:/Documents and Settings/rbaer/Desktop/_VNT_Test/coordFocused 20k F5 0ng Ki8751 t20.txt"
I have 2 questions:
1. Is it possible to get file.choose() to use the forward slash rather than the escaped...
2014 May 29
0
EFI & grub on a Dell PowerEdge T20...
OK, I have installed CentOS 6.5 on this beast using parted to make GPT
partitions (royal PIA, but done). The machine has three 500G SATA disks with
4K sector sizes.
Partitioned with three partions for each of the main disks:
sda1 => FAT32 => /boot/efi
sdb1 => FAT32 => (not presently mounted, but will be a backup copy of
/boot/efi).
sda2, sdb2 => /dev/md0
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...dd t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
t16: ch = llvm.tpu.dma.write.1KB.async t0,
TargetConstant:i32<4602>, t10, t12, t15
t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
t20: i32 = AssertZext t18, ValueType:ch:i1
t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396
t28: i1 = setcc t25, Constant:i32<255>, setugt:ch
t29: i1 = and t23, t28
t37: i1 = setcc t29, Constant:...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...FromReg t0, Register:i32 %vreg79
>> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
>> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15
>> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
>> t20: i32 = AssertZext t18, ValueType:ch:i1
>> t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
>> t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396
>> t28: i1 = setcc t25, Constant:i32<255>, setugt:ch
>> t29: i1 = and t23, t28...
2007 Mar 01
2
[LLVMdev] Version 1.9 SSA form question
...t12 = or uint %.t11, %.t8 ; <uint> [#uses=2]
%.t15 = shr uint %.t12, ubyte 8 ; <uint> [#uses=1]
%.t16 = or uint %.t15, %.t12 ; <uint> [#uses=2]
%.t19 = shr uint %.t16, ubyte 16 ; <uint>
[#uses=1]
%.t20 = or uint %.t19, %.t16 ; <uint> [#uses=1]
%.t22 = mul uint %.t20, 116069625 ; <uint>
[#uses=1]
%.t25 = shr uint %.t22, ubyte 26 ; <uint>
[#uses=1]
%.t28 = getelementptr [64 x ubyte]* %table, int 0, uint %.t25
; <ub...
2009 Sep 29
1
How to parsing data like this in R
Hi, R-users,
I met a problem:
Items:[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11]/Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t0\t12\t18\t00\t00\t11/Elina 'Konsertissa. En tod. vastaa teille'\tEtu-Töölö, Helsinki (2:40)\t24\t12\t18\t00\t00\t11
I want to parsing the above data into the below according to each "/&...
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...ectionDAG has 15 nodes:
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t10: i32 = and t2, Constant:i32<65535>
t16: i64 = zero_extend t10
t17: i64 = ctlz t16
t22: i64 = add t17, Constant:i64<-32>
t20: i32 = truncate t22
t15: i32 = add t20, Constant:i32<-16>
t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15
t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1
It seems that SelectionDAG::computeKnownBits() has a case for ISD::CTLZ,
and it seems to figure out that the high...
2005 Jul 12
1
Bug report
as everyone deserves to know when things go wrong:
i'm trying to flash the bios on my IBM T20 laptop. i've got a floppy image, and am attempting to use memdisk with grub to boot it via the following:
title Flash T20 Bios
root (hd0,0)
kernel /memdisk root=/dev/md0
initrd /T20_flash_floppy.img
that much WORKS.
the interesting part is that the system becomes unresponsive RIGHT AFTER...
2014 May 31
1
CentOS 6 KVM networking: What am I missing???
OK, I have a strange problem. It is probably something simple/stupid, but I
cannot figure it out.
I have a nice new PowerEdge T20 that I installed CentOS 6 (6.5) on with
Virtualization (KVM). I then installed Ubuntu 14.04 in a virtual machine,
with a bridged network:
------ begin ub140464.xml------------------
<domain type='kvm' id='2'>
<name>ub140464</name>
<uuid>53f7caec-1ff8-...
2003 Oct 07
4
Beginner's query - segmentation fault
...currently displayed as
the value "-999.00" I am trying to create a new matrix (or change the
existing one) to display these values as "NA" so that I can then perform
the necessary analysis on the columns within the matrix.
The matrix name is temp and the column names are t1 to t20 inclusive.
I have tried the following command:
temp$t1[temp$t1 == -999.00] <- NA
and it returns a segmentation fault, can someone tell me what I am doing
wrong?
Thanks
Laura
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...t;, Constant:i64<1>,
Constant:i64<2>, Constant:i64<3>, Constant:i64<4>, Constant:i64<5>, Constant:i64<6>,
Constant:i64<7>
t16: v8i64 = add t7, t15
t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16
t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t22: i64 = AssertSext t20, ValueType:ch:i8
t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0>
t24: v8i64 = vector_shuffle<0,0,0,0,0,0,0,0> t23, undef:v8i64...
2018 Apr 09
1
llvm-dev Digest, Vol 166, Issue 22
...ant:i32<0> // [a]
t21: v2i16 = extract_subvector t2, Constant:i32<2> //[c d]
t22: i16 = extract_vector_elt t21, Constant:i32<0> // [c]
t25: v2i16 = BUILD_VECTOR t27, t22 // [a c]
t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25
t19: ch = RTN t18
t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1
Creating new node: t28: v2i16 = undef
Creating new node: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16
After reduceBuildVecToShuffle
SelectionDAG has 16 nodes:
t0: ch = EntryToken
t2: v4i16,ch = CopyFromReg t0, Register:v4i...
2018 Jul 03
2
Question about canonicalizing cmp+select
...> enabling another hook) to transform the sext+add into shift+or? I think the
> answer is 'yes'. We probably should add that fold. This seems like a
> similar case as the recent: https://reviews.llvm.org/D48466
>
> Note that on x86, the sext+add becomes zext+sub:
> t20: i8 = setcc t3, Constant:i16<-1>, setgt:ch
> t24: i16 = zero_extend t20
> t17: i16 = sub Constant:i16<5>, t24
>
> Would that transform help your target?
>
> On Tue, Jul 3, 2018 at 3:55 PM, Yuan Lin <yualin at google.com> wrote:
>
>> Hi, Roman a...
2016 Jan 25
2
Instruction selection gives "LLVM ERROR: Cannot select"
...}
!3 = distinct !{!3, !4, !5}
!4 = !{!"llvm.loop.vectorize.width", i32 1}
!5 = !{!"llvm.loop.interleave.count", i32 1}
!6 = distinct !{!6, !2}
!7 = distinct !{!7, !4, !5}
I get the following error:
LLVM ERROR: Cannot select: t21: ch = store<ST64[%6](align=4)> t20, t19, t6, undef:i64
I don't understand why because it seems to me store is specified well in
[MyTarget]InstrInfo.td .
Can somebody help with an idea? Myself I will try to debug the code generated with
TableGen, implementing the function SelectCode() .
Best regards,
Ale...
2008 Jun 25
6
To upgrade or not
My laptop is a Thinkpad T20 running CentOS 5.1
The reason it is running CentOS at all is because Fedora Core 6 was
workable on it, but Fedora 8 was a complete dog.
Anyway - with all the new desktop stuff in CentOS 5.2 I'm wondering if I
would be happier just leaving it at 5.1 rather than letting it update to
5.2.
Wi...
2011 Feb 20
2
concatenate vector after strsplit()
...uot;µm"), c("Focused", "10k", "A12",
"t12.tif", "+", "µm"), c("Focused", "10k", "A12", "t16.tif",
"+", "µm"), c("Focused", "10k", "A12", "t20.tif", "+", "µm"),
c("Focused", "10k", "A12", "t24.tif", "+", "µm"), c("Focused",
"10k", "A12", "t36.tif", "+", "µm"), c("Focused", &qu...
2018 Jul 03
4
Question about canonicalizing cmp+select
Hi, Sanjay/all,
I noticed in rL331486 that some compare-select optimizations are disabled
in favor of providing canonicalized cmp+select to the backend.
I am currently working on a private backend target, and the target has a
small code size limit. With this change, some of the apps went over the
codesize limit. As an example,
C code:
b = (a > -1) ? 4 : 5;
ll code:
Before rL331486:
2004 Jan 26
7
Problem with FreeDOS + himem64 + PXELINUX + memdisk
...EMM386:
http://www.ibiblio.org/pub/micro/pc-stuff/freedos/files/dos/emm386/
I am comparing it with fdxxms.sys, part of FDXMS:
http://www.ibiblio.org/pub/micro/pc-stuff/freedos/files/dos/fdxms/
When I use PXELINUX+memdisk (version 2.08) to boot a trivial FreeDOS
boot disk on my IBM Thinkpad T20, using "DEVICE=himem64.exe" in
config.sys, the system spontaneously reboots after reading config.sys
and printing this message:
Kernel allocated 42 Diskbuffers = 22344 Bytes in HMA
This problem only happens on the T20; it does not happen on my other
test system (Dell Optiplex GX200)....
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type is 'v2i1'. If the size of vector element is less than 8bit,
'DAGTypeLegalizer::SplitVe...