Displaying 2 results from an estimated 2 matches for "t1xhae".
2020 Jul 20
2
[ARM] Should Use Load and Store with Register Offset
...iced that LLVM does not tend to generate load/store
instructions with a register offset (e.g. ldr Rd, [Rn, Rm] form) and
instead prefers the immediate offset form.
When copying a contiguous sequence of bytes, this results in additional
instructions to modify the base address. https://godbolt.org/z/T1xhae
void* memcpy_alt1(void* dst, const void* src, size_t len) {
char* save = (char*)dst;
for (size_t i = 0; i < len; ++i)
*((char*)(dst + i)) = *((char*)(src + i));
return save;
}
clang --target=armv6m-none-eabi -Os -fomit-frame-pointer
memcpy_alt1:
push {r4, lr}...
2020 Jul 21
2
[ARM] Should Use Load and Store with Register Offset
...tend to generate load/store
> instructions with a register offset (e.g. ldr Rd, [Rn, Rm] form) and
> instead prefers the immediate offset form.
>
> When copying a contiguous sequence of bytes, this results in additional
> instructions to modify the base address. https://godbolt.org/z/T1xhae
>
> void* memcpy_alt1(void* dst, const void* src, size_t len) {
> char* save = (char*)dst;
> for (size_t i = 0; i < len; ++i)
> *((char*)(dst + i)) = *((char*)(src + i));
> return save;
> }
>
> clang --target=armv6m-none-eabi -Os -fomit-frame-pointe...