Displaying 8 results from an estimated 8 matches for "t1_xyzw".
2014 Feb 25
4
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
Hi Tom,
Thanks a lot for your explanations, now it makes a lot more sense ;)
I had a slightly closer look at the R600 packetizer, and the issue is
that the third LSHL instruction has both an implicit use and
*afterwards* an implicit def of T1_XYZW. The latter def causes the
current ScheduleDAGInstrs implementation to ignore the implicit use,
thus the ScheduleDAG only contains an anti-dependency from the second to
the third LSHL and the packetizer can bundle the instructions.
If the order of the implicit-defs and implicit-use would be dif...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ne code for function main: Post SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
0BBB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%T1_W<def> = KILL %T1_W, %T1_XYZW<imp-def>
32B%T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
48B%T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
64B%T1_X<def> = KILL %T1_X, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
128B%T2_X<def>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> 0BBB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> 16B%T1_W<def> = KILL %T1_W, %T1_XYZW<imp-def>
> 32B%T1_Z<def> = KILL %T1_Z, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
> 48B%T1_Y<def> = KILL %T1_Y, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
> 64B%T1_X<def> = KILL %T1_X, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
>...
2014 Feb 25
2
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
...struction bundles" pass:
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
%T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def>
%T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
Hence, my patch affects either the R600 Packetizer or the R600 Control Flow Finalizer pa...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...B,1056r:0) 0 at 480r
LHS = %vreg48 [416r,448B:0)[448B,480r:1)[1120r,1168B:2) 0 at 416r 1 at 448B-phi 2 at 1120r
merge %vreg6:0 at 480r into %vreg48:1 at 448B --> @448B
erased:480r%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
AllocationOrder(R600_Reg128) = [ %T0_XYZW %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW %T5_XYZW %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW %T13_XYZW %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW %T21_XYZW %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW %T29_XYZW %T30_XYZW %T31_XYZW %T32_XY...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg48 [416r,448B:0)[448B,480r:1)[1120r,1168B:2) 0 at 416r 1 at 448B-phi
> 2 at 1120r
> merge %vreg6:0 at 480r into %vreg48:1 at 448B --> @448B
> erased:480r%vreg6<def> = COPY %vreg48<kill>;
> R600_Reg128:%vreg6,%vreg48
> AllocationOrder(R600_Reg128) = [ %T0_XYZW %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW
> %T5_XYZW %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW
> %T13_XYZW %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW
> %T21_XYZW %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW
> %T29_XYZW %T3...
2012 Sep 27
1
[LLVMdev] Setting cl::opt<bool> EnablePhysicalJoin without a command line
...e for function main: Post SSA, not tracking liveness
Function Live Ins: %T2_X in %vreg0, %T1_W in %vreg1, %T1_Z in %vreg2, %
T1_Y in %vreg3, %T1_X in %vreg4
BB#0: derived from LLVM BB %main_body
Live Ins: %T2_X %T1_W %T1_Z %T1_Y %T1_X
%T1_X<def,undef> = KILL %T1_X<kill,undef>, %T1_XYZW<imp-def,undef>
R600_Export
%T1_XYZW<kill>, 0, 0, 0, 1, 2, 3
%T2_X<def,undef> = KILL %T2_X<kill,undef>, %T2_XYZW<imp-def,undef>
R600_Export_DONE %T2_XYZW<kill>, 0, 61, 2, 7, 7, 7
RETURN
# End machine code for function main.
whereas when set to fa...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...%vreg9:sel_x
RHS = %vreg6 [112r,160r:0) 0 at 112r
LHS = %vreg9 [160r,176r:0) 0 at 160r
merge %vreg9:0 at 160r into %vreg6:0 at 112r --> @112r
erased:160r%vreg9:sel_x<def,read-undef> = COPY %vreg6<kill>; R600_Reg128:%vreg9 R600_Reg32:%vreg6
AllocationOrder(R600_Reg128) = [ %T0_XYZW %T1_XYZW %T2_XYZW %T3_XYZW %T4_XYZW %T5_XYZW %T6_XYZW %T7_XYZW %T8_XYZW %T9_XYZW %T10_XYZW %T11_XYZW %T12_XYZW %T13_XYZW %T14_XYZW %T15_XYZW %T16_XYZW %T17_XYZW %T18_XYZW %T19_XYZW %T20_XYZW %T21_XYZW %T22_XYZW %T23_XYZW %T24_XYZW %T25_XYZW %T26_XYZW %T27_XYZW %T28_XYZW %T29_XYZW %T30_XYZW %T31_XYZW %T32_XY...