Displaying 20 results from an estimated 33 matches for "t18".
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2009 Sep 29
1
How to parsing data like this in R
Hi, R-users,
I met a problem:
Items:[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11]/Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t0\t12\t18\t00\t00\t11/Elina 'Konsertissa. En tod. vastaa teille'\tEtu-Töölö, Helsinki (2:40)\t24\t12\t18\t00\t00\t11
I want to parsing the above data into the below according to each "/":
[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t...
2018 Apr 09
1
llvm-dev Digest, Vol 166, Issue 22
...Constant:i32<0> // [a b]
t27: i16 = extract_vector_elt t26, Constant:i32<0> // [a]
t21: v2i16 = extract_subvector t2, Constant:i32<2> //[c d]
t22: i16 = extract_vector_elt t21, Constant:i32<0> // [c]
t25: v2i16 = BUILD_VECTOR t27, t22 // [a c]
t18: ch,glue = CopyToReg t0, Register:v2i16 %m0, t25
t19: ch = RTN t18
t20: ch = RTN_REG_HOLDER t19, Register:v2i16 %m0, t18:1
Creating new node: t28: v2i16 = undef
Creating new node: t29: v2i16 = vector_shuffle<0,0> t26, undef:v2i16
After reduceBuildVecToShuffle
SelectionDAG has...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...t9: i32 = shl t4, Constant:i32<2>
t10: i32 = add t6, t9
t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
t16: ch = llvm.tpu.dma.write.1KB.async t0,
TargetConstant:i32<4602>, t10, t12, t15
t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
t20: i32 = AssertZext t18, ValueType:ch:i1
t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396
t28: i1 = setcc t25, Constant:i32<255>, setugt:ch...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...gt;> t10: i32 = add t6, t9
>> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79
>> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1
>> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15
>> t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166
>> t20: i32 = AssertZext t18, ValueType:ch:i1
>> t23: i1 = setcc t20, Constant:i32<0>, seteq:ch
>> t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396
>> t28: i1 = setcc t25, Co...
2016 Dec 22
2
struct bitfield regression between 3.6 and 3.9 (using -O0)
...DAG has the AND op node:
t22: i8 = srl t19, Constant:i64<1>
* t23: i8 = and t22, Constant:i8<1>*
t24: i32 = zero_extend t23
t27: i1 = setcc t24, Constant:i32<1>, seteq:ch
t29: i1 = xor t27, Constant:i1<-1>
t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48>
t33: ch = br t31, BasicBlock:ch<if.then 0xa5f8c98>
The Optimized lowered selection DAG does not contain the* AND* node, but it
does have a truncate which would seem to stand in for it given the result
is only 1bit wide and the xor following it i...
2016 Dec 22
0
struct bitfield regression between 3.6 and 3.9 (using -O0)
...; t22: i8 = srl t19, Constant:i64<1>
> * t23: i8 = and t22, Constant:i8<1>*
> t24: i32 = zero_extend t23
> t27: i1 = setcc t24, Constant:i32<1>, seteq:ch
> t29: i1 = xor t27, Constant:i1<-1>
> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48>
> t33: ch = br t31, BasicBlock:ch<if.then 0xa5f8c98>
>
> The Optimized lowered selection DAG does not contain the*AND* node,
> but it does have a truncate which would seem to stand in for it given
> the result is only 1bit wide a...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...gister:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type is ...
2017 Feb 07
3
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64
...duced by this simple program:
>
> thread_local int x = 0;
> int main() {
> return 0;
> }
>
>When compiled into IR it produces similar error:
>
>LLVM ERROR: Cannot select: t19: i64 = X86ISD::WrapperRIP
TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=19]
> t18: i64 = TargetGlobalTLSAddress<i32* @x> 0 [TF=19]
>In function: _ZTW1x
interestingly this works on my machine.
llvm-ir attached
2017-02-07 15:31 GMT+00:00 Alex Denisov <1101.debian at gmail.com>:
> I’ve seen the same problem, but didn’t find solution back then.
> I can giv...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...undef:v8i64
t15: v8i64 = BUILD_VECTOR Constant:i64<0>, Constant:i64<1>,
Constant:i64<2>, Constant:i64<3>, Constant:i64<4>, Constant:i64<5>, Constant:i64<6>,
Constant:i64<7>
t16: v8i64 = add t7, t15
t18: ch = CopyToReg t0, Register:v8i64 %vreg16, t16
t20: i64,ch = CopyFromReg t0, Register:i64 %vreg5
t22: i64 = AssertSext t20, ValueType:ch:i8
t23: v8i64 = insert_vector_elt undef:v8i64, t22, Constant:i64<0>...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...gt; t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
> t31: ch = TokenFactor t24, t27
> t13: v2i1 = setcc t8, t11, setne:ch
> t16: i1 = extract_vector_elt t13, t15
> t17: i32 = extract_vector_elt t8, t15
> t18: i32 = extract_vector_elt t11, t15
> t19: i1 = setcc t17, t18, setne:ch
> t20: i1 = xor t16, t19
>
> ...
>
> I have not added any vector register class so 'DAGTypeLegalizer' tries
> to split the "t16: i1 = extract_vector_elt t13, t15" becaus...
2016 Dec 23
2
struct bitfield regression between 3.6 and 3.9 (using -O0)
...; t22: i8 = srl t19, Constant:i64<1>
> * t23: i8 = and t22, Constant:i8<1>*
> t24: i32 = zero_extend t23
> t27: i1 = setcc t24, Constant:i32<1>, seteq:ch
> t29: i1 = xor t27, Constant:i1<-1>
> t31: ch = brcond t18, t29, BasicBlock:ch<if.else 0xa5f8d48>
> t33: ch = br t31, BasicBlock:ch<if.then 0xa5f8c98>
>
> The Optimized lowered selection DAG does not contain the* AND* node, but
> it does have a truncate which would seem to stand in for it given the
> result is only 1bit wide an...
2016 Apr 29
3
Assert in TargetLoweringBase.cpp
This post is related to the following post
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html
I'm still trying to compile a library with clang. But now I'm getting as
assert in
lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT
llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT)
const: Assertion `!VT.isVector() && "No default
2018 Apr 30
0
[SelectionDAG] DbgValue nodes aren't transferred
...!14
%call = tail call i16 (...) @g() #2, !dbg !15
tail call void @llvm.dbg.value(metadata i16 %call, metadata !8, metadata !16), !dbg !17
tail call void @h(i16 %call) #2, !dbg !18
ret void, !dbg !19
}
For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0.
t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11
t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11
t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:1...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...gister:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type i...
2018 Apr 30
2
[SelectionDAG] DbgValue nodes aren't transferred
...g() #2, !dbg !15
> tail call void @llvm.dbg.value(metadata i16 %call, metadata !8, metadata !16), !dbg !17
> tail call void @h(i16 %call) #2, !dbg !18
> ret void, !dbg !19
> }
>
> For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0.
>
> t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11
> t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11
> t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, te...
2018 Mar 15
1
[SelectionDAG] DbgValue nodes aren't transferred
...t;
> From: jdevlieghere at apple.com <jdevlieghere at apple.com>
> Sent: Wednesday, March 14, 2018 4:07 AM
> To: Se Jong Oh <sejooh at microsoft.com>
> Cc: Vedant Kumar <vsk at apple.com>; llvm-dev at lists.llvm.org; Adrian Prantl <aprantl at apple.com>; pidgeot18 at gmail.com
> Subject: Re: [llvm-dev] [SelectionDAG] DbgValue nodes aren't transferred
>
> Hi Sejong,
>
> Indeed, I think you are right and we should call transferDbgValues in SetPromotedInteger.
>
> I couldn’t immediately find a suitable in-tree test to verify this...
2020 Jul 05
8
[RFC] carry-less multiplication instruction
<div> </div><div><div><p>Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious, <code>llvm.experimental.bitmanip.clmul</code> instruction.
2017 Feb 07
2
[cfe-dev] lli: LLVM ERROR: Cannot select: X86ISD::WrapperRIP TargetGlobalTLSAddress:i64
+ LLVM-dev (clang is mostly about the frontend and this is a backend failure), you may have more change to get an answer.
> On Feb 6, 2017, at 5:49 AM, Gaetano Checinski via cfe-dev <cfe-dev at lists.llvm.org> wrote:
>
> Running the following code with clang++ -S -emit-llvm main.cpp && lli main.ll on Linux(Debian)
>
> #include <future>
>
> int main () {
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...gister:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector register class so 'DAGTypeLegalizer' tries
to split the "t16: i1 = extract_vector_elt t13, t15" because t13's
result type i...
2019 Jun 02
2
Optimizing Compare instruction selection
...tion call,
t30: i16 = CMPkr16 t4, TargetConstant:i16<0>
t36: ch,glue = CopyToReg t0, Register:i16 $sr, t30
t32: i16 = NEGSETCC TargetConstant:i16<4>, t36:1
And this is generated after the call
t35: ch,glue = CopyToReg t0, Register:i16 $sr, t30
t31: i16 = SELCC t19, t18, TargetConstant:i16<4>, t35:1
t21: ch,glue = CopyToReg t18:1, Register:i16 $r0, t31
NEGSETCC and SELCC are genuine instructions of my target architecture, they use the SR along with operands to produce a result.
As you can see ‘t30’ is used both before and after the function call, which...