Displaying 20 results from an estimated 43 matches for "t14".
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2006 Jun 07
2
help with combination problem
hello:
I have 3 data.frame objects.
First df object:
Of dim (149,31). Columns 2:31 are marked as T1..T14
and N1..N16.
Name T1 T2 N1 T3 N2 N3 N4 T4
mu1 10 10 9 10 9 9 8 10
mu2 11 11 9 11 9 9 9 11
...
muN 12 12 9 11 9 9 8 12
Second df object:
of Dim (50000,31). Columns 2:31 are maked as T1...T14
and N1..N16.
Name...
2024 Jan 29
1
linear programming in R | limits to what it can do, or my mistake?
...pically, the LHS) since each line of said
matrix, which corresponds to the constraints, needs to be a function of
the unknowns in the objective function -- being, p1, p2, p3 and p4.
In Maple (for example), this is trivial:
???? cost:=35*p10+55*p12+50*p14+65*p16;
cnsts:={t10=640,t12=t10-p10+825,t14=t12-p12+580,t16=t14-p14+925,t16-p16=0,p10<=t10,p12<=t12,p14<=t14,p16<=t16,t10<=1000,t12<=1000,t14<=1000,t16<=1000};
? ?? Minimize(cost,cnsts,assume={nonnegative});
which yields (correctly):
p1=640, p2=405, p3=1000, p4=925
for minimized cost of 154800.
Took only a minute...
2024 Jan 30
1
linear programming in R | limits to what it can do, or my mistake?
...of said
> matrix, which corresponds to the constraints, needs to be a function of
> the unknowns in the objective function -- being, p1, p2, p3 and p4.
>
> In Maple (for example), this is trivial:
>
> ???? cost:=35*p10+55*p12+50*p14+65*p16;
> cnsts:={t10=640,t12=t10-p10+825,t14=t12-p12+580,t16=t14-p14+925,t16-p16=0,p10<=t10,p12<=t12,p14<=t14,p16<=t16,t10<=1000,t12<=1000,t14<=1000,t16<=1000};
> ? ?? Minimize(cost,cnsts,assume={nonnegative});
>
> which yields (correctly):
>
> p1=640, p2=405, p3=1000, p4=925
>
> for minimized...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7,
> t12, undef:i64
> t7: v64i32 = add t6, t4
> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
> undef:i64
> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x
> i32]* @c> 0
> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
> t3: i64 = undef
> t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64...
2017 Jul 06
2
Error in v64i32 type in x86 backend
...t10: ch = store<ST256[bitcast ([65 x i32]* @a to
<64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
t7: v64i32 = add t6, t4
t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
t3: i64 = undef
t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
i32>*)](align=16)(tbaa=<0x30c5438>)(derefer...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...65 x i32]* @a
>> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>> t7: v64i32 = add t6, t4
>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
>> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
>> t3: i64 = undef
>> t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
>> i32>...
2009 Apr 18
4
Loop question
...I thought at
first:
t1<-matrix(0, nrow=250, ncol=1)
for(i in 1:10){
t1[i]<-rnorm(250)
}
What I intended was that the loop would create 10 different matrices
with a single column of 250 values randomly selected from a normal
distribution, and that they would be labeled t11, t12, t13, t14 etc.
Can anyone steer me in the right direction with this one?
Thanks!
Brendan
2016 Oct 20
2
[AVX512BW] Nasty KAND issue
...>, the
result is undefined unless the unused bits are zero. You can see this in
the debug output from llc:
SelectionDAG has 15 nodes:
t0: ch = EntryToken
t21: i32 = X86ISD::KORTEST t19, t19
t22: i8 = X86ISD::SETCC Constant:i8<4>, t21
t23: i32 = zero_extend t22
t14: ch,glue = CopyToReg t0, Register:i32 %EAX, t23
t24: i16,ch = load<LD1[%XXX](align=4)(dereferenceable), zext from
i8> t0, FrameIndex:i64<0>, undef:i64
t26: i16 = AssertZext t24, ValueType:ch:i4
t19: v16i1 = bitcast t26
t15: ch = X86ISD::RET_FLAG t14, TargetConstant:i3...
2018 Apr 09
2
A way to opt out of a dag combine?
...nert for in
tree targets.
Given a v4f16 instance t2, the DAG describes building a v2f16 vector from
elements [0, 2]. The combine translates this to building a vector from
elements [0, 0]. The problem seems to be treating extract_subvector with
different constants as instances of the same value.
t14: v2f16 = extract_subvector t2, Constant:i32<2>
t15: f16 = extract_vector_elt t14, Constant:i32<0>
t16: v2f16 = extract_subvector t2, Constant:i32<0>
t17: f16 = extract_vector_elt t16, Constant:i32<0>
t9: v2f16 = BUILD_VECTOR t17, t15
... into: t19: v2f16 = vector_shu...
2008 Apr 16
0
ZFS raidz1 replacing failing disk
...RADED 0 0 0
c3t9d0s0 ONLINE 0 0 0
c3t10d0s0 ONLINE 0 0 0
c3t12d0s0 ONLINE 0 0 0
spare DEGRADED 0 0 0
c3t13d0s0 OFFLINE 0 0 0
c3t14d0s0 ONLINE 0 0 0
spares
c3t14d0s0 INUSE currently in use
errors: No known data errors
As you can see, the t13 disk is offline and physically removed.
The machine is still very slow.
I want to remove the t13 disk from the zpool, but I can''t.
My q...
2016 Sep 07
2
Receiving LLVM Error in Custom Backend
Hi,
I am receiving an LLVM Error from a custom 16-bit backend I am creating. I
am having trouble understanding the error/problem and how to go about
solving it. The error is:
LLVM ERROR: Cannot select: t29: i32,ch = load<LD2[%x.addr], anyext from
i16> t14, FrameIndex:i16<0>, undef:i16
t7: i16 = FrameIndex<0>
t9: i16 = undef
In function: mul_add
Can anyone provide any pointers as to what the problem is and potential
places I should look to fix it?
Thanks and best regards,
Mush
-------------- next part --------------
An HTML attach...
2010 Jul 23
2
start and end times to yes/no in certain intervall
...3:00", "13:00", "13:00", "13:00",
"13:00", "13:00")), .Names = c("start", "end"), row.names = c(NA,
20L), class = "data.frame")
and I would like the data to look like this:
> t9 t10 t11 t12 t13 t14 t15 t16 t17
> 1 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 2 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 3 FALSE FALSE FALSE FALSE FALSE FALSE TRUE FALSE FALSE
> 4 FALSE FALSE TRUE FALSE FALSE FALSE FALSE FALSE FALSE
> 5 FALSE FALSE FALSE FALSE F...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...o <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>>>> t7: v64i32 = add t6, t4
>>>> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
>>>> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14,
>>>> undef:i64
>>>> t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]*
>>>> @c> 0
>>>> t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
>>>> t3: i64 = undef
>>>> t4: v64i32,ch =...
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
...gt; t0, t5, undef:i16
Creating new node: t10: i16,ch = CopyFromReg t0, Register:i16 %2
Creating new node: t11: i16 = add t10, t4
Creating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16
Creating constant: t13: i16 = Constant<1>
Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1>
Creating new node: t16: ch = CopyToReg t0, Register:i16 %1, t14
Creating new node: t17: ch = TokenFactor t16, t12
Creating new node: t19: ch = br t17, BasicBlock:ch<for.cond 0x10983ff38>
Initial selection DAG: %bb.3 'tst:for.body'
Selection...
2009 Feb 19
0
change the label size when drawing trees with ape
...4):40.08);"
t10 =
"((1:54.81,3:54.81):13.81,(2:64.24,4:64.24):4.38000000000001);"
t11 =
"((1:61.44,3:61.44):26.94,(2:26.52,4:26.52):61.86);"
t12 =
"((1:11.05,(3:10.15,4:10.15):0.9):68.71,2:79.76);"
t13 =
"(((1:39.53,3:39.53):6.25,4:45.78):3.09,2:48.87);"
t14 =
"((1:55.12,(2:37.99,3:37.99):17.13):18.28,4:73.4);"
t15 =
"((1:73.39,(2:54.24,4:54.24):19.15):20.58,3:93.97);"
library(ape)
ft = c(5,5,5,5)
postscript("test.ps")
par(mfrow=c(5,3))
plot(read.tree(text=t1),font=ft)
plot(read.tree(text=t2),font=ft)
plot(read.tree(tex...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...egister:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>
... into: t15: i64 = rotl Constant:i64<-2>, t6
Combining: t10: i64 = and t2, t15
Combining: t15: i64 = rotl Constant:i64<-2>, t6
Combining: t14: i64 = Constant<-2>
Combining: t6: i64 = sub t4, Constant:i64<1>
... into: t17: i64 = add t4, Constant:i64<-1>
Combining: t15: i64 = rotl Constant:i64<-2>, t17
These rotl instructions weren't showing up when I ran llc 3.6 and that's
completely changing the gene...
2019 Sep 27
4
Dealing with boolean values in GlobalISel
...all boolean sourced intrinsics.
For example, in this function:
define i32 @foo(i32 %a, i32 %b, i32 %c) {
%cc = trunc i32 %a to i1
%r = select i1 %cc, i32 %b, i32 %c
ret i32 %r
}
SelectionDAG legalizes this to:
t0: ch = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t14: i32 = and t2, Constant:i32<1>
t4: i32,ch = CopyFromReg t0, Register:i32 %1
t6: i32,ch = CopyFromReg t0, Register:i32 %2
t8: i32 = select t14, t4, t6
t10: ch,glue = CopyToReg t0, Register:i32 $w0, t8
t11: ch = AArch64ISD::RET_FLAG t10, Register:i32 $w0, t10:1
Such that th...
2023 Nov 27
1
Apps moving to laptop display when switching KVM
So I installed CentOS Stream 9 on a new Lenovo T14 Gen 4 Intel.
I have a 4x1 HDMI KVM with external monitor.
When switching the KVM, apps move between displays / workspaces in erratic ways.
More specifically, when switching out, apps on the external display
usually move to the laptop display.
This sorta makes sense for a laptop with an external...
2016 Oct 20
2
[AVX512BW] Nasty KAND issue
On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote:
>
>> On Oct 20, 2016, at 8:54 AM, Cameron McInally via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> Hey guys,
>>
>> I've hit a pretty nasty issue on SKX with ANDs of masks <= 4 bits.
>>
>> In the IR, we represent a 4b vector mask as <4 x i1>.
2016 Apr 16
2
[TSAN] LLVM statistics and pass initialization trigger race detection
....cpp:50 (libLTO.dylib+0x000000ab2e8e)
#4 (anonymous namespace)::SimpleInliner::SimpleInliner() InlineSimple.cpp:49 (libLTO.dylib+0x000000ab2d19)
#5 llvm::createFunctionInliningPass() InlineSimple.cpp:85 (libLTO.dylib+0x000000ab2ce3)
...
Previous read of size 4 at 0x0001113619e8 by thread T14:
#0 llvm::initializeSimpleInlinerPass(llvm::PassRegistry&) InlineSimple.cpp:82 (libLTO.dylib+0x000000ab2b65)
#1 (anonymous namespace)::SimpleInliner::SimpleInliner() InlineSimple.cpp:50 (libLTO.dylib+0x000000ab2e8e)
#2 (anonymous namespace)::SimpleInliner::SimpleInliner() InlineSimp...