Displaying 20 results from an estimated 86 matches for "t13".
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2016 Jun 22
2
LLVM Backend Issues
...ore<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>,
undef:i32
t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>,
FrameIndex:i32<3>, undef:i32
t12: ch = store<ST4[%m]> t10, Constant:i32<0>, FrameIndex:i32<19>,
undef:i32
t13: i32,ch = load<LD4[%sz]> t12, FrameIndex:i32<2>, undef:i32
t15: ch = store<ST4[%j]> t13:1, t13, FrameIndex:i32<16>, undef:i32
t17: ch = store<ST4[%le]> t15, t13, FrameIndex:i32<14>, undef:i32
Optimized lowered selection DAG: BB#0 'main:entry'
Sele...
2016 Jun 21
3
LLVM Backend Issues
Hi,
I am having issues running a new backend that I created for a new
architecture. I suspect these errors may have something to do with how I
have the string setup in LLVMTargetMachine() below?
Also - It would be great if someone could point me to a document that
describes some of these error messages? For example what does t26 ..t4 mean?
Thanks in advance for taking your valuable time to help
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...-23>
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector reg...
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
...4,ch,glue = CopyFromReg t0, Register:i64 %reg0
t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1
t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1
t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1
t11: ch = CopyToReg t0, Register:i64 %vreg0, t2
t13: ch = CopyToReg t0, Register:i64 %vreg1, t4
t15: ch = CopyToReg t0, Register:i64 %vreg2, t8
t26: ch = TokenFactor t11, t13, t15, t2:1, t4:1, t6:1, t8:1
t16: i64 = sdiv t2, t4
Before legalization, there is a single sdiv node. After legalization, this
has been expanded to a call...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ch = CopyFromReg t0, Register:i32 %vreg2
> t22: i32 = add t15, Constant:i32<1>
> t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
> t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
> t31: ch = TokenFactor t24, t27
> t13: v2i1 = setcc t8, t11, setne:ch
> t16: i1 = extract_vector_elt t13, t15
> t17: i32 = extract_vector_elt t8, t15
> t18: i32 = extract_vector_elt t11, t15
> t19: i1 = setcc t17, t18, setne:ch
> t20: i1 = xor t16, t19
>
> ...
>...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...r:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...Register:i64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>>
>> Combining: t11: i64 = Register %R1
>>
>> C...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...r:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...-23>
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...6: i64 = sub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>
> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>
> Combining: t11: i64 = Register %R1
>
>...
2013 Dec 16
4
[PATCH 1/2] Match comment with code
..."EF" partition
> typed IDs in relation to EFI, but not about "ED" (in relation to
> EFI). Perhaps I am just misunderstanding this email thread (?).
That's what I thought, and I haven't found any reference to ED, except for
doc/gpt.txt which talks about "the T13-approved protocol for GPT partitions with BIOS
firmware."
>
> TIA,
> Ady.
Kind regards,
Ruben
2013 Dec 16
2
[PATCH 1/2] Match comment with code
...s in relation to EFI, but not about "ED" (in relation to
> >> EFI). Perhaps I am just misunderstanding this email thread (?).
> >
> > That's what I thought, and I haven't found any reference to ED, except for
> > doc/gpt.txt which talks about "the T13-approved protocol for GPT partitions with BIOS
> > firmware."
> >
>
> Yes, it is in the T13 EDD documentation.
>
> -hpa
Here is what I found.
24 July 2009 (older)
e09127r0
"EDD-4 Hybrid MBR support"
[/quote]
Set to the OS Type field of the Partition Re...
2009 Apr 18
4
Loop question
...what I thought at
first:
t1<-matrix(0, nrow=250, ncol=1)
for(i in 1:10){
t1[i]<-rnorm(250)
}
What I intended was that the loop would create 10 different matrices
with a single column of 250 values randomly selected from a normal
distribution, and that they would be labeled t11, t12, t13, t14 etc.
Can anyone steer me in the right direction with this one?
Thanks!
Brendan
2006 Jun 27
1
Boxplot questions.
Dear all,
I am having a data for 2 different treatments with
different time points. So, I used the following code
to plot the boxplot and also to do anova.
T11 <- c(280, 336, 249, 277, 429)
T12 <- c(400, 397, 285, 407, 313)
T13 <- c(725, 373, 364, 706, 249)
T21 <- c(589, 257, 466, 248, 913)
T22 <- c(519, 424, 512, 298, 907)
T23 <- c(529, 479, 634, 354, 1015)
obs <- c(T11, T12, T13, T21, T22, T23)
treat <- c(rep("T1",15), rep("T2",15))
time <- c(rep("one",5), rep("t...
2003 May 06
1
Slow disk access on Dell Latitute with ATA/ATAPI-5 T13 1321D
Hi...
I have a Dell Latitute with an ATA/ATAPI-5 T13 1321D and it would seem
that my disk access is extremely slow. I have the latest updated kernel
from RedHat 8.0 kernel 2.4.18-27.8.0. Somehow I think it is related to
the UDMA stuff (shows my level of understanding). I have run hdparm and
although I think I should at least udma level 5, I have...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...-23>
t15: i32,ch = CopyFromReg t0, Register:i32 %vreg2
t22: i32 = add t15, Constant:i32<1>
t24: ch = CopyToReg t0, Register:i32 %vreg3, t22
t27: ch = CopyToReg t0, Register:i32 %vreg8, Constant:i32<-1>
t31: ch = TokenFactor t24, t27
t13: v2i1 = setcc t8, t11, setne:ch
t16: i1 = extract_vector_elt t13, t15
t17: i32 = extract_vector_elt t8, t15
t18: i32 = extract_vector_elt t11, t15
t19: i1 = setcc t17, t18, setne:ch
t20: i1 = xor t16, t19
...
I have not added any vector...
2020 Feb 22
2
COPYs between register classes
Hi,
On SystemZ there are a set of "access registers" that can be copied in
and out of 32-bit GPRs with special instructions. These instructions can
only perform the copy using low 32-bit parts of the 64-bit GPRs. As
reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254,
this is currently broken due to the fact that the default register class
for 32-bit integers is
2018 Dec 18
2
In ISel, where Constant<0> comes from?
...lt;(store 4 into %ir.retval)> t0, Constant:i32<0>,
FrameIndex:i64<0>, undef:i64
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t11: ch = store<(store 4 into %ir.argc.addr)> t9, t2,
FrameIndex:i64<1>, undef:i64
t4: i64,ch = CopyFromReg t0, Register:i64 %1
t13: ch = store<(store 8 into %ir.argv.addr)> t11, t4,
FrameIndex:i64<2>, undef:i64
t16: ch,glue = CopyToReg t13, Register:i32 $eax, Constant:i32<0>
t17: ch = X86ISD::RET_FLAG t16, TargetConstant:i32<0>, Register:i32 $eax, t16:1
where the t16 line corresponds to what you'...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...2-i64:64-n32:32-S128". I also gave at the end of
ConnexTargetLowering::ConnexTargetLowering() the following:
ValueTypeActions.setTypeAction(MVT::i16, TypeLegal);
to avoid errors like:
Promote integer operand: t16: ch = store<ST256[inttoptr (i16 250 to <128 x i16>*)]>
t13:1, t13, Constant:i16<250>, undef:i16
But even now it gives errors like:
ISEL: Starting pattern match on root node: t16: ch = store<ST256[inttoptr (i16 250
to <128 x i16>*)]> t13:1, t13, Constant:i16<250>, undef:i16
Initial Opcode index to 157
Skipp...
2013 Dec 17
1
[PATCH 1/2] Match comment with code
...; I wonder whether other documents / standards explicitly mention *any*
> > partition ID, and whether these IDs could potentially result in
> > future inconsistencies / problems / bugs / hours of tracking down
> > strange (mis)behaviors.
> >
>
> You're right - T13 changed the "OS Type" from 0xED to "that would have
> been assigned had the partition been installed in an MBR disk layout".
> That is kind of hard to accomplish without blowing the MBR code size
> budget, since it effectively requires a mapping from GUIDs to OS types....