search for: t10

Displaying 20 results from an estimated 95 matches for "t10".

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2016 Nov 03
2
rotl: undocumented LLVM instruction?
...as 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combinin...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...i64,ch = CopyFromReg t0, Register:i64 %vreg0 >> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 >> t6: i64 = sub t4, Constant:i64<1> >> t7: i64 = shl Constant:i64<1>, t6 >> t9: i64 = xor t7, Constant:i64<-1> >> t10: i64 = and t2, t9 >> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 >> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 >> >> >> >> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 >> >> Combining: t12: ch,glue = CopyToReg t0,...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...as 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 Combining: t11: i64 = Register %R1 Combinin...
2007 Nov 29
3
lustre osd implementation
hello, does lustre support OSD T10 standard? Can it be used with IBM''s/Intel''s OSD initiator and target? Thanks, Ashish -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.lustre.org/pipermail/lustre-discuss/attachments/20071128/c2de31a6/...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...reg0 > t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 > t6: i64 = sub t4, Constant:i64<1> > t7: i64 = shl Constant:i64<1>, t6 > t9: i64 = xor t7, Constant:i64<-1> > t10: i64 = and t2, t9 > t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10 > t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 > > > > Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1 > > Combining: t12: ch,glue...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...p this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166...
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
...0: ch = EntryToken >> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 >> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6, t9 >> t12: i32,ch = CopyFromReg t0, Register:i32 %vreg79 >> t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 >> t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 >> t18: i32,ch = CopyF...
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
...nction: define i16 @fun(i16 %arg) {   %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)   ret i16 %1 } ,gives this optimized DAG as input to instruction selection: SelectionDAG has 15 nodes:   t0: ch = EntryToken                 t2: i32,ch = CopyFromReg t0, Register:i32 %0               t10: i32 = and t2, Constant:i32<65535>             t16: i64 = zero_extend t10           t17: i64 = ctlz t16         t22: i64 = add t17, Constant:i64<-32>       t20: i32 = truncate t22     t15: i32 = add t20, Constant:i32<-16>   t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15...
2018 Sep 21
2
[PATCH] vhost/scsi: truncate T10 PI iov_iter to prot_bytes
On Wed, Aug 22, 2018 at 01:21:53PM -0600, Greg Edwards wrote: > Commands with protection information included were not truncating the > protection iov_iter to the number of protection bytes in the command. > This resulted in vhost_scsi mis-calculating the size of the protection > SGL in vhost_scsi_calc_sgls(), and including both the protection and > data SG entries in the protection
2017 Jul 07
2
Error in v64i32 type in x86 backend
...s. > > in order to do this i have made necessary changes in > X86ISelLowering.cpp. and rebuild llvm. then when i use the > command -view-dag-combine2-dags i get the required output in graph > but the following error on console: > > LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x > i32]* @a to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, > t12, undef:i64 > t7: v64i32 = add t6, t4 > t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x > i32>*)](align=16)(tbaa=&lt...
2019 Jun 05
2
Strange behaviour of post-legalising optimisations(?)
...ating new node: t4: i16,ch = CopyFromReg t0, Register:i16 %0 Creating new node: t5: i16 = add t2, t4 Creating constant: t6: i16 = Constant<0> Creating new node: t7: i16 = undef Creating new node: t8: i8,ch = load<(load 1 from %ir.scevgep1, !tbaa !2)> t0, t5, undef:i16 Creating new node: t10: i16,ch = CopyFromReg t0, Register:i16 %2 Creating new node: t11: i16 = add t10, t4 Creating new node: t12: ch = store<(store 1 into %ir.scevgep, !tbaa !2)> t8:1, t8, t11, undef:i16 Creating constant: t13: i16 = Constant<1> Creating new node: t14: i16 = add nuw nsw t4, Constant:i16<1...
2017 Jul 07
2
Error in v64i32 type in x86 backend
...ns. >> >> in order to do this i have made necessary changes in X86ISelLowering.cpp. >> and rebuild llvm. then when i use the command -view-dag-combine2-dags i >> get the required output in graph but the following error on console: >> >> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a >> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64 >> t7: v64i32 = add t6, t4 >> t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x >> i32>*)](align=16)(tbaa=<0x30c543...
2017 Sep 21
1
VSelect Instruction Error
Hello, I am getting this error. What instruction is required to be implemented? LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16 t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64 t659: i64 = FrameIndex<1> t10: i64 = undef t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0, t8, undef:i64 t8: i64 = add t7, Constant:i64<4> t7: i64 = add t2, t63 t2: i64,ch = CopyFromReg t0, Register:i64 %vreg97 t1: i64 = Register %vreg97 t63: i64 =...
2010 May 27
10
A couple of questions
Hi, I''ve been looking at Btrfs and have a couple of naive questions that don''t seem to be answered on the wiki or in the articles I''ve read on the filesystem. First: discovering a file''s checksum value. Here''s the scenario: software is writing some data as a fresh file. This software happens to know (a priori) the checksum of this data; for
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
...t5: i16,ch = load<Volatile LD2[%1](align=1)(dereferenceable)> t0, t2, undef:i16 t7: ch,glue = CopyToReg t5:1, Register:i16 %R25R24, t5 t8: ch = RET_FLAG t7, Register:i16 %R25R24, t7:1 The resulting output is SelectionDAG has 8 nodes: t0: ch = EntryToken t7: ch,glue = CopyToReg t10:1, Register:i16 %R25R24, t10 t2: i16,ch = CopyFromReg t0, Register:i16 %vreg0 t9: i16,i16,ch = LDWRdPtr<Mem:Volatile LD2[%1](align=1)(dereferenceable)> t2, t0 t10: i16,ch,i16 = merge_values t9, t9:2, t9:1 t8: ch = RET Register:i16 %R25R24, t7, t7:1 As you can see, even though...
2020 Apr 01
2
[RFC] [Windows SEH] Local_Unwind (Jumping out of a _finally) and -EHa (Hardware Exception Handling)
...+= 1; if (abnormal_termination()) { printf(" inner finally: exception path \n\r"); } else { printf(" inner finally: normal path \n\r"); } if (lu) { printf(" inner finally: local unwind \n\r"); goto t10; } printf(" inner finally: normal return \n\r"); } } finally { Counter += 1; printf(" outer finally: \n\r"); } } except(Counter) { /* set counter = 3 */ printf(" except handler: \n\r"); Counter += 1; } printf(&quo...
2020 Apr 02
2
[RFC] [Windows SEH] Local_Unwind (Jumping out of a _finally) and -EHa (Hardware Exception Handling)
...mp" to target label. This is why it's called "local_unwind()", depending on the EH state of the target, local_unwind() runtime invokes _finally properly alone the way to final target. Again, take the case #2 as example, the outer _finally must be invoked before control goes to $t10. ? To be clear, we're talking about making all memory accesses, including accesses to local variables, in the try block "volatile"? So the compiler can't do any optimization on them? That gets you some fraction of the way there; there are no issues with SSA registers if there...
2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...dereferenceable since its loading from one of the TargetFrames. Am I on the right track here? Thanks Sean -------------- next part -------------- Initial selection DAG: BB#0 '_Z3fn2v:entry' SelectionDAG has 122 nodes: t4: i64 = GlobalAddress<void (%class.F*)* @_Z10EmitLValuev> 0 t10: i64 = add Register:i64 %X1, Constant:i64<32> t0: ch = EntryToken t3: ch = lifetime.start t0, TargetFrameIndex:i64<1> t7: ch,glue = callseq_start t3, TargetConstant:i64<32>, TargetConstant:i64<0> t12: ch,glue = CopyToReg t7, Register:i64 %X3, FrameIndex:i...
2010 May 05
1
Does Opensolaris support thin reclamation?
Support for thin reclamation depends on the SCSI "WRITE SAME" command; see this draft of a document from T10: http://www.t10.org/ftp/t10/document.05/05-270r0.pdf. I spent some time searching the source code for support for "WRITE SAME", but I wasn''t able to find much. I assume that if it was supported, it would be listed in this header file: http:/...
2007 Nov 30
1
lustre-1.8 OSD
lustre-1.8 has OSD structures in place, what do I need to add in to make it work with OSD T10 standard? could anybody point me to some docs mentioning lustre internals - OSTs, OSSs, OBDs, and control flow when a read/write call is invoked by a client. thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.lustre.org/pipermail/...