search for: t0_w

...ference is the '*' in the second LSHL and the T0.W versus PV.W in the third LSHL. Looking at the output of -print-after-all, llc generates the following MC in both plain LLVM 3.4 and LLVM 3.4 with my patch applied right after the "Finalize machine instruction bundles" pass: %T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0 %T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def> %T1_W<def&...

...econd LSHL and the T0.W versus PV.W in the third LSHL. >> >> Looking at the output of -print-after-all, llc generates the following MC in both plain LLVM 3.4 and LLVM 3.4 with my patch applied right after the "Finalize machine instruction bundles" pass: >> >> %T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0 >> %T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def> >&gt...

...t;kill>, 0, pred:%noreg, %T0_XYZW<imp-def> %T2_X<def> = KILL %T2_X<kill>, %T2_XYZW<imp-def> %T0_Y<def> = MOV %T1_Y<kill>, 0, pred:%noreg, %T0_XYZW<imp-def> %T0_Z<def> = MOV %T1_Z<kill>, 0, pred:%noreg, %T0_XYZW<imp-def> %T0_W<def> = MOV %T1_W<kill>, 0, pred:%noreg, %T0_XYZW<imp-def> R600_Export %T0_XYZW<kill>, 0, 0, 0, 1, 2, 3 R600_Export_DONE %T2_XYZW<kill>, 0, 61, 2, 7, 7, 7 RETURN # End machine code for function main. Of course this is a rather simple code, but shaders ofte...

...:0)  0 at 464r LHS = %vreg47 [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at 448B-phi 2 at 1104r merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B erased:464r%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47 AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y %T11_Z %T11_W %T12_X %T12_Y %T12_Z %T12_W...

...7 [400r,448B:0)[448B,464r:1)[1104r,1168B:2)  0 at 400r 1 at 448B-phi > 2 at 1104r > merge %vreg5:0 at 464r into %vreg47:1 at 448B --> @448B > erased:464r%vreg5<def> = COPY %vreg47<kill>; > R600_Reg32:%vreg5,%vreg47 > AllocationOrder(R600_Reg32) = [ %T0_X %T0_Y %T0_Z %T0_W %T1_X %T1_Y %T1_Z %T1_W > %T2_X %T2_Y %T2_Z %T2_W %T3_X %T3_Y %T3_Z %T3_W %T4_X %T4_Y %T4_Z %T4_W %T5_X > %T5_Y %T5_Z %T5_W %T6_X %T6_Y %T6_Z %T6_W %T7_X %T7_Y %T7_Z %T7_W %T8_X %T8_Y > %T8_Z %T8_W %T9_X %T9_Y %T9_Z %T9_W %T10_X %T10_Y %T10_Z %T10_W %T11_X %T11_Y > %T11_Z %T11_W %T1...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2