search for: synthetised

...like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA). In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent. VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is co...

...any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA). > In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent. Does this 'concurrency' mean that we need to figure out data-independent instructions in VHDL? Although LLVM-IR is written serially, its SSA...

doc/swfdec-sections.txt | 3 + libswfdec/Makefile.am | 1 libswfdec/swfdec.h | 1 libswfdec/swfdec_as_object.c | 1 libswfdec/swfdec_key.h | 32 ++++++++++++++ libswfdec/swfdec_marshal.list | 1 libswfdec/swfdec_player.c | 83 +++++++++++++++++++++++++++++++++++-- libswfdec/swfdec_player.h |

...any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA). > In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent. Does this 'concurrency' mean that we need to figure out data-independent instructions in VHDL? Although LLVM-IR is written serially, its SSA...

libswfdec-gtk/swfdec_gtk_widget.c | 19 libswfdec/swfdec_as_object.c | 56 +- libswfdec/swfdec_as_object.h | 4 libswfdec/swfdec_button.c | 228 +++++++++ libswfdec/swfdec_button.h | 10 libswfdec/swfdec_button_movie.c | 382