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...gt;> Before we settle on whether this is the right thing to do or not, can >> you talk about what comments you plan to add to these instructions? >> Comments indicating what a memoperand are (for example) don't need to >> be explicitly store in the machineinstr, they can be synthesized from >> the MachineOperand directly. > > Some things we've used comments for: > > - Tag instructons with source line information (customers really > want this). Right, that would be nice. This should be synthesizable from the DebugLoc on the instruction in the asm p...

...ad and do it. > Before we settle on whether this is the right thing to do or not, can > you talk about what comments you plan to add to these instructions? > Comments indicating what a memoperand are (for example) don't need to > be explicitly store in the machineinstr, they can be synthesized from > the MachineOperand directly. Some things we've used comments for: - Tag instructons with source line information (customers really want this). - Tag instructions as register spills or reloads. - Tag instructions as top-of-loop, with nesting information (we use this to do some...

...t; Makes sense, thanks. Please do it as a separate patch from the other > changes though since it will be large and mechanical. Ok, no problem. > > - Tag instructons with source line information (customers really > > want this). > > Right, that would be nice. This should be synthesizable from the > DebugLoc on the instruction in the asm printer, no need to redundantly > encode it into the comment field. Except the DebugLoc stuff isn't all there yet AFAIK. We've been using the comment mechanism for over a year. I agree we should move to synthesizing it from Deb...

...rs (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. TCE has been developed internally in the Department of Computer Systems of Tampere University of Technology since the early 2003...

...rs (ASP) based on the Transport Triggered Architecture (TTA). TTA is a minimalistic processor architecture template that allows high level of control for the designer to choose the boundary between the hardware and the software. The toolset provides a complete codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. TCE has been developed internally in the Department of Computer Systems of Tampere University of Technology since the early 2003...

Announcing the Release of TTA-Based Codesign Environment (TCE) v1.2 TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. New features since the last release include LLVM 2.7 support with Clang as the default compiler frontend, Altera MIF-format supp...

...released -------------------------------------------------- TTA-Based Codesign Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable codesign flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. Notable new features -------------------- - Support for LLVM 2.8 (support for LLVM 2.7 retained) - ttasim: call info (setting pr...

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. This release includes support for LLVM 3.0, experimental OpenCL C Embedded Profile support (in offline compilation/standalone mo...

...---------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. This release adds support for LLVM 3.1, experimental Verilog backend for the Proc...

...subject, I'd like to ask you if you can forward this email to him/her. The OpenCores organization announces the immediate availability of the open-source, free, complete 33/66MHz 32-bit PCI Bridge Soft Core solution. PCI Bridge Complete & Tested The PCI Bridge Soft Core is a complete, synthesizable RTL (Verilog) code that provides bridging between the PCI and a WISHBONE (System-on-Chip) bus. The complete package includes comprehensive specification and design documentation, a comprehensive verification suite, and a test application. Test application is a ?VGA card? implemented using a...

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. Release Highlights ================== - Support for LLVM 5.0. - Support for lit...

TTA-based Co-design Environment (TCE) is a toolset for design and programming of low power customized processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog generation supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. Release Highlights ================== - Support for LLVM 6.0. - Sane defaults...

TTA-Based Co-design Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network. This release includes support for LLVM 2.9, some new VHDL implementations (an FPU and streaming operations), a connectivity opti...

...onment (TCE) is a semi-automated toolset developed at the Tampere University of Technology for designing processors based on an easily customizable Transport Triggered Architecture (TTA) processor architecture template. The toolset provides a complete co-design toolchain from program source code to synthesizable hardware design and program binaries. One of the most important tools in the toolchain is the compiler. The compiler is required to adapt to customized target architectures and to utilize the available processor resources as efficiently as possible and still produce programs with correct be...

On Jul 13, 2009, at 10:02 AM, David Greene wrote: >>> - Tag instructons with source line information (customers really >>> want this). >> >> Right, that would be nice. This should be synthesizable from the >> DebugLoc on the instruction in the asm printer, no need to >> redundantly >> encode it into the comment field. > > Except the DebugLoc stuff isn't all there yet AFAIK. We've been > using the > comment mechanism for over a year. I agree we...

...more harm than good. People using `-ffreestanding` are now expecting the compiler to call these functions, inlining bloat can be problematic for the embedded world ( see comments in https://reviews.llvm.org/D60719 ) *Proposals* We envision two approaches: an *attribute to prevent the compiler from synthesizing calls* or a *set of builtins* to communicate the intent more precisely to the compiler. 1. A function/module attribute to disable synthesis of calls 1.1 A specific attribute to disable the synthesis of a single call __attribute__((disable_call_synthesis("memcpy"))) Question: Is...