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2006 Jun 05
0
Idct - fpga - improved
Good news,
Working with synchrounous RAM (fpga internal SRAM blocks) the area
usage drop from 20% to 5% of Logic Cells.
And the clock frequency from 30 Mhz to 90 Mhz.
Now I'm improving the latency of samples (number of clock cycles
needed to decode a data sample).
Report:
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Fitter Status : Successful - Mon Jun 5...