search for: synchroniz

Displaying 9 results from an estimated 9 matches for "synchroniz".

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2008 May 30
2
Web-based shared calendar synchronizable with Outlook
Hi, I know this request is a a little off-topic but may be interesting for dovecot users (at least i hope!) Does anybody has already had an experience with a calendar sharing solution including a webcalendar and an outlook connector, "compatible" with dovecot ? Today, there are many projects aiming to be a "M$ Exchange Killer" (such as Zimbra, OBM, open-exchange, etc) but
2007 Aug 24
2
error in rails 1.2.3 activerecord
...1.8/gems/rake-0.7.2/lib/rake.rb:399:in `each'' c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rake-0.7.2/lib/rake.rb:399:in `execute'' c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rake-0.7.2/lib/rake.rb:369:in `invoke'' c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rake-0.7.2/lib/rake.rb:362:in `synchroniz e'' c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rake-0.7.2/lib/rake.rb:362:in `invoke'' c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rails-1.2.3/lib/tasks/databases.rake:76 c:/ruby186/ruby/lib/ruby/gems/1.8/gems/rake-0.7.2/lib/rake.rb:399:in `call'' c:/ruby186/ruby/lib/ruby/gems/1.8/ge...
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...nstruction completes" provides the equivalent > of ARM/Power A-cumulativity, which can be thought of as transitivity > backwards in time. I couldn't make that leap. In particular, the manual's "Detailed Description" sections explicitly refer to program-order: Every synchronizable specified memory instruction (loads or stores or both) that occurs in the instruction stream before the SYNC instruction must reach a stage in the load/store datapath after which no instruction re-ordering is possible before any synchronizable specified memory instruction which occurs a...
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...nstruction completes" provides the equivalent > of ARM/Power A-cumulativity, which can be thought of as transitivity > backwards in time. I couldn't make that leap. In particular, the manual's "Detailed Description" sections explicitly refer to program-order: Every synchronizable specified memory instruction (loads or stores or both) that occurs in the instruction stream before the SYNC instruction must reach a stage in the load/store datapath after which no instruction re-ordering is possible before any synchronizable specified memory instruction which occurs a...
2005 Dec 16
11
mysql mem-tables vs. memcached
...e elaborate on the technical differences and practical impact of whether choosing memory-based tables in MySQL or using memcached. I got this far on my own: It seems that MySQL uses the NDB engine for transaction-safe memory access in a cluster. the memory storage engine seems to be faster but not synchronizable by any means in a cluster. memcached seems to be ultimately fast but requires extra effort in your code. Who got experience on that? Best regards Peter
2016 Jan 15
0
[v3,11/41] mips: reuse asm-generic/barrier.h
...the equivalent > > of ARM/Power A-cumulativity, which can be thought of as transitivity > > backwards in time. > > I couldn't make that leap. In particular, the manual's "Detailed > Description" sections explicitly refer to program-order: > > Every synchronizable specified memory instruction (loads or stores or > both) that occurs in the instruction stream before the SYNC > instruction must reach a stage in the load/store datapath after which > no instruction re-ordering is possible before any synchronizable > specified memory instru...
2016 Jan 14
3
[v3,11/41] mips: reuse asm-generic/barrier.h
On 01/14/2016 01:29 PM, Paul E. McKenney wrote: > >> On 01/14/2016 12:34 PM, Paul E. McKenney wrote: >>> >>> The WRC+addr+addr is OK because data dependencies are not required to be >>> transitive, in other words, they are not required to flow from one CPU to >>> another without the help of an explicit memory barrier. >> I don't see any
2016 Jan 14
3
[v3,11/41] mips: reuse asm-generic/barrier.h
On 01/14/2016 01:29 PM, Paul E. McKenney wrote: > >> On 01/14/2016 12:34 PM, Paul E. McKenney wrote: >>> >>> The WRC+addr+addr is OK because data dependencies are not required to be >>> transitive, in other words, they are not required to flow from one CPU to >>> another without the help of an explicit memory barrier. >> I don't see any
2006 Mar 24
1
R crashes when loading library/package; Windows, Cygwin
...enable-nls --without-included-gettext --enable-version-specific-runt ime-libs --without-x --enable-libgcj --disable-java-awt --with-system-zlib --ena ble-interpreter --disable-libgcj-debug --enable-threads=posix --enable-java-gc=b oehm --disable-win32-registry --enable-sjlj-exceptions --enable-hash-synchroniza tion --enable-libstdcxx-debug : (reconfigured) Thread model: posix gcc version 3.4.4 (cygming special) (gdc 0.12, using dmd 0.125) $ perl -v This is perl, v5.8.8 built for MSWin32-x86-multi-thread (with 21 registered patches, see perl -V for more detail) Copyright 1987-2006, Larry Wall Binary...