search for: sycling

Hi all, We'd like to some SYCL tests to LLVM's test suite. The SYCL support in the LLVM repo is still very much a work-in-progress, but since the test-suite is supposed to be able to support compilers other than clang, I thought it would be reasonable to start adding the tests there now, disabled by default, rather than maintaining a fork of the test-suite repo until SYCL support is fully

Thanks, Johannes! It would be nice to have some additional infrastructure to control execution of tests that have special resource requirements like this. We've seen some problems in our internal testing with parallel test execution causing system gridlock. Having a common way to address that would be great. One reason I thought separate SYCL folders (either at the top level or elsewhere in

Hi Johannes, The structure you suggested makes sense to me. Vladimir Lazarev has been working on moving some end-to-end tests out of the source tree (in the intel/llvm GitHub branch where the parts of our SYCL development that aren’t ready to be included in the main LLVM repo are being shared). He has a local working copy that can run the tests with various hardware and device runtimes. The last

That’s a good question. I’m afraid I don’t know how/if that’s controlled in these tests. From: Johannes Doerfert <johannesdoerfert at gmail.com> Sent: Monday, June 08, 2020 3:05 PM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Lazarev, Vladimir <vladimir.lazarev at intel.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org>; bhomerding at anl.gov; Finkel, Hal J.

I have code like this: data <- read.csv("test1.csv", stringsAsFactors=FALSE, header=TRUE) # Graph myplot=ggplot(data, aes(fill=condition, y=value, x=condition)) + geom_bar(position="dodge", stat="identity", width=0.5) + scale_fill_manual(values=c("#7b3294", "#c2a5cf", "#a6dba0", "#008837"))+

Hi, I have a data frame like this: > dput(df) structure(list(ID = 1:8, Type = c("gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps 10000 -resethway", "gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps 10000 -resethway", "gmx mdrun -ntmpi 8 -s benchPEP.tpr -nsteps 4000 -resetstep 3000", "gmx mdrun -ntmpi 8 -s benchPEP.tpr -nsteps 4000 -resetstep

Thank you so much David, here is correction: d1=suppressWarnings(read.csv("/Users/anamaria/Downloads/B1.csv", stringsAsFactors=FALSE, header=TRUE)) d1$X <- NULL d2=as.matrix(sapply(d1, as.numeric)) pdf("~/graph.pdf") b<-barplot(d2, legend= c("SYCL", "CUDA"), beside= TRUE,las=2,cex.axis=0.7,cex.names=0.7,ylim=c(0,80), col=c("#9e9ac8",

Hello, I have a data frame like this: d11=suppressWarnings(read.csv("/Users/anamaria/Downloads/B1.csv", stringsAsFactors=FALSE, header=TRUE)) > d11 X Domain.decomp. DD.com..load Neighbor.search Launch.PP.GPU.ops. Comm..coord. 1 SYCL 2. 1 0 3.7 0. 1 1 .6 2 CUDA 2 0 3. 1 0 1 .0

Hi all, Recently I do some jobs based on llvm-link tool. I wonder why link '@llvm.global_ctors' into dest file, even it's not used in dest file? And how can I remove it? Thank you all in advance! Fangqing Xilinx Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL:

I am already successfully generating SPIR-V with a forward port of Khronos’ SPIR-V LLVM. What does one need in order to generate SPIR? From what I gather it is based on a specific LLVM IR version (3.4?) with a bunch of metadata. Is it possible to generate SPIR from LLVM trunk? If so how? Thanks Nic -------------- next part -------------- An HTML attachment was scrubbed... URL:

HI LLVM comunity, after 3 years of development, various talks on LLVM-HPC and EuroLLVM and other scientific conferences I want to present my PhD research topic to the lists. The main goal for my research was to develop a single-source programming model equal to CUDA or SYCL for accelerators supported by LLVM (e.g., Nvidia GPUs). PACXX uses Clang as front-end for code generation and comes with

On Thu, Jan 16, 2020 at 12:16:30PM -0800, Ralph Campbell wrote: > Can you point me to the latest ODP code? Seems like my understanding is > quite off. https://elixir.bootlin.com/linux/v5.5-rc6/source/drivers/infiniband/hw/mlx5/odp.c Look for the word 'implicit' mlx5_ib_invalidate_range() releases the interval_notifier when there are no populated shadow PTEs in its leaf

On 7/28/20 3:03 PM, Renato Golin wrote: > On Tue, 28 Jul 2020 at 20:44, Johannes Doerfert > <johannesdoerfert at gmail.com> wrote: >> What I (tried to) describe is that you can pass an array of structs via >> a CUDA memcpy (or similar) to the device and then expect it to be >> accessible as an array of structs on the other side. I can imagine this >>

Interesting. I do something similar for D targeting CUDA (via NVPTX) and OpenCL (via my forward proved fork of Khronos’ SPIRV-LLVM)[1], except all the code generation is done at compile time. The runtime is aided by compile time reflection so that calling kernels is done by symbol. What kind of performance difference do you see running code that was not developed with GPU in mind (e.g.

I was going to say, this reminds me of Kai's presentation at Fosdem yesterday. https://fosdem.org/2018/schedule/event/heterogenousd/ It's always good to see the cross-architecture power of LLVM being used in creative ways! :) cheers, --renato On 5 February 2018 at 13:35, Nicholas Wilson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Interesting. > > I do something

Page 22 of OpenMP 5.0 specification (Lines 13/14): When any thread encounters a simd construct, the iterations of the loop associated with the construct may be executed concurrently using the SIMD lanes that are available to the thread This is the Execution Model. The word here is "may" i.e., not "must". Declare simd is not explicitly mentioned here, but requiring

Hi, we are looking for either one post-doctoral researcher or PhD student to work with us on the CELERITY project. The main goal is the design of a programming environment to develop energy- and performance- efficient, predictably scalable, and easy-to-program parallel applications targeting large-scale heterogeneous HPC clusters. The CELERITY environment will integrate a compilation part

Hi all, I'm trying to get the llvm's IR from the source code of Polybench (OMP) https://github.com/cavazos-lab/PolyBench-ACC/tree/master/OpenMP. I noticed a considerable difference between the IR generated using clang -emit-llvm -fopenmp and clang -emit-llvm: * using the -fopenmp flag I get a simplified IR in which I read a single basic block where I can highlight a llvm.memcpy

Motivation === Over the last decade we have developed an interactive, interpretative C++ (aka REPL) as part of the high-energy physics (HEP) data analysis project -- ROOT [1-2]. We invested a significant  effort to replace the CINT C++ interpreter with a newly implemented REPL based on llvm -- cling [3]. The cling infrastructure is a core component of the data analysis framework of ROOT and

>Is this also the case if the user did require lock-step semantic for the code to be correct? Certainly not, but that part is actually beyond OpenMP specification. I suggest looking up ICC's "#pragma simd assert" description and see if the assert feature is something you may be interested in seeing as an extended part of LLVM implementation of OpenMP (declare) simd. Else,