search for: sycl

Hi all, We'd like to some SYCL tests to LLVM's test suite. The SYCL support in the LLVM repo is still very much a work-in-progress, but since the test-suite is supposed to be able to support compilers other than clang, I thought it would be reasonable to start adding the tests there now, disabled by default, rather than main...

...me additional infrastructure to control execution of tests that have special resource requirements like this. We've seen some problems in our internal testing with parallel test execution causing system gridlock. Having a common way to address that would be great. One reason I thought separate SYCL folders (either at the top level or elsewhere in the tree) would be useful is that I think we'll probably want a single option to turn these tests on or off as a group. A "parallel" folder may make sense for the same reason. I see your point about mixed languages, but perhaps we could...

Hi Johannes, The structure you suggested makes sense to me. Vladimir Lazarev has been working on moving some end-to-end tests out of the source tree (in the intel/llvm GitHub branch where the parts of our SYCL development that aren’t ready to be included in the main LLVM repo are being shared). He has a local working copy that can run the tests with various hardware and device runtimes. The last version of this that I saw put the tests in llvm-test-suite/SYCL, but it should be easy enough to move them an...

...ists.llvm.org>; bhomerding at anl.gov; Finkel, Hal J. <hfinkel at anl.gov>; Kruse, Michael <michael.kruse at anl.gov>; Malik,Abid <amalik at bnl.gov>; Clement, Valentin <clementv at ornl.gov>; Neeraj Ganu <neeraj.ganu at stonybrook.edu> Subject: Re: [cfe-dev] Adding SYCL tests in test-suite Sounds great. Did he also put in nobs to limit parallelism, make sure not to oversubscribe the system, etc. ? On 6/8/20 4:53 PM, Kaylor, Andrew wrote: Hi Johannes, The structure you suggested makes sense to me. Vladimir Lazarev has been working on moving some end-to-e...

...NM_WATER.tpr -nsteps 10000", "gmx mdrun -gpu_id 1 -ntomp 16 -s MD_15NM_WATER.tpr -nsteps 10000", "gmx mdrun -gpu_id 1 -ntomp 16 -s MD_15NM_WATER.tpr -nsteps 10000", "gmx mdrun -gpu_id 1 -ntomp 16 -s MD_15NM_WATER.tpr -nsteps 10000"), condition = c("Tesla P100-SYCL", "Tesla V100-SYCL", "Tesla P100-CUDA", "Tesla V100-CUDA", "Tesla P100-SYCL", "Tesla V100-SYCL", "Tesla P100-CUDA", "Tesla V100-CUDA"), value = c(75.8, 77.771, 63.297, 78.046, 34.666, 50.052, 32.07, 59.815)), class = "d...

..., "gmx mdrun -ntmpi 8 -s benchPEP.tpr -nsteps -1 -maxh 1.0 -resethway", "gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps -1 -maxh 1.0 -resethway -noconfout", "gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps -1 -maxh 1.0 -resethway -noconfout" ), Annee = c("SYCL", "CUDA", "SYCL", "CUDA", "SYCL", "CUDA", "SYCL", "CUDA"), Domain.decomp. = c("2. 1", "2", "2. 1", "2. 1", "2.1", "2", "2. 1", "2"), DD.com..loa...

Thank you so much David, here is correction: d1=suppressWarnings(read.csv("/Users/anamaria/Downloads/B1.csv", stringsAsFactors=FALSE, header=TRUE)) d1$X <- NULL d2=as.matrix(sapply(d1, as.numeric)) pdf("~/graph.pdf") b<-barplot(d2, legend= c("SYCL", "CUDA"), beside= TRUE,las=2,cex.axis=0.7,cex.names=0.7,ylim=c(0,80), col=c("#9e9ac8", "#6a51a3")) dev.off() > dput(head(d1)) structure(list(Domain.decomp. = c("2. 1", "2"), DD.com..load = c(0L, 0L), Neighbor.search = c("3.7", &...

Hello, I have a data frame like this: d11=suppressWarnings(read.csv("/Users/anamaria/Downloads/B1.csv", stringsAsFactors=FALSE, header=TRUE)) > d11 X Domain.decomp. DD.com..load Neighbor.search Launch.PP.GPU.ops. Comm..coord. 1 SYCL 2. 1 0 3.7 0. 1 1 .6 2 CUDA 2 0 3. 1 0 1 .0 Force Wait...Comm..F PIE.mesh Wait.Bonded.GPU wait.GPU.NB.nonloc. 1 1 . 5 1 .3 65.6 0 0 2 1 .2...

Hi all, Recently I do some jobs based on llvm-link tool. I wonder why link '@llvm.global_ctors' into dest file, even it's not used in dest file? And how can I remove it? Thank you all in advance! Fangqing Xilinx Inc. -------------- next part -------------- An HTML attachment was scrubbed... URL:

I am already successfully generating SPIR-V with a forward port of Khronos’ SPIR-V LLVM. What does one need in order to generate SPIR? From what I gather it is based on a specific LLVM IR version (3.4?) with a bunch of metadata. Is it possible to generate SPIR from LLVM trunk? If so how? Thanks Nic -------------- next part -------------- An HTML attachment was scrubbed... URL:

HI LLVM comunity, after 3 years of development, various talks on LLVM-HPC and EuroLLVM and other scientific conferences I want to present my PhD research topic to the lists. The main goal for my research was to develop a single-source programming model equal to CUDA or SYCL for accelerators supported by LLVM (e.g., Nvidia GPUs). PACXX uses Clang as front-end for code generation and comes with a runtime library (PACXX-RT) to execute kernels on the available hardware. Currently, PACXX supports Nvidia GPUs through the NVPTX Target and CUDA, CPUs through MCJIT (including...

On Thu, Jan 16, 2020 at 12:16:30PM -0800, Ralph Campbell wrote: > Can you point me to the latest ODP code? Seems like my understanding is > quite off. https://elixir.bootlin.com/linux/v5.5-rc6/source/drivers/infiniband/hw/mlx5/odp.c Look for the word 'implicit' mlx5_ib_invalidate_range() releases the interval_notifier when there are no populated shadow PTEs in its leaf

...penMP. The compiler cannot know what your memory actually is because types are, you know, just hints for the most part. So we need the devices to match the host data layout wrt. padding, alignment, etc. or we could not copy an array of structs from one to the other and expect it to work. CUDA, HIP, SYCL, ... should all be the same. I hope someone corrects me if I have some misconceptions here :) >> I think that a multi-DL + multi-triple design seems like a good >> candidate. > > I agree. Multiple-DL is something that comes and goes in the community > and so far the &quo...

...> HI LLVM comunity, > > after 3 years of development, various talks on LLVM-HPC and EuroLLVM and other scientific conferences I want to present my PhD research topic to the lists. > > The main goal for my research was to develop a single-source programming model equal to CUDA or SYCL for accelerators supported by LLVM (e.g., Nvidia GPUs). PACXX uses Clang as front-end for code generation and comes with a runtime library (PACXX-RT) to execute kernels on the available hardware. Currently, PACXX supports Nvidia GPUs through the NVPTX Target and CUDA, CPUs through MCJIT (including...

...M comunity, >> >> after 3 years of development, various talks on LLVM-HPC and EuroLLVM and other scientific conferences I want to present my PhD research topic to the lists. >> >> The main goal for my research was to develop a single-source programming model equal to CUDA or SYCL for accelerators supported by LLVM (e.g., Nvidia GPUs). PACXX uses Clang as front-end for code generation and comes with a runtime library (PACXX-RT) to execute kernels on the available hardware. Currently, PACXX supports Nvidia GPUs through the NVPTX Target and CUDA, CPUs through MCJIT (including...

...in LoopVectorize) and I think that's what you are asking. If so, we are aligned. If anyone strongly goes against that idea (i.e., anyone wanting to keep OpenMP simd as just an optimization hint for auto-vectorizer), please speak up. >if you think there is a problem to reuse that for OpenCL/SYCL, let us know. Sure. -----Original Message----- From: Doerfert, Johannes [mailto:jdoerfert at anl.gov] Sent: Friday, May 31, 2019 4:58 PM To: Saito, Hideki <hideki.saito at intel.com> Cc: Francesco Petrogalli <Francesco.Petrogalli at arm.com>; Philip Reames <listmail at philipreame...

...edictably scalable, and easy-to-program parallel applications targeting large-scale heterogeneous HPC clusters. The CELERITY environment will integrate a compilation part (based on LLVM), a distributed runtime system, and a set of advanced modeling approaches. The programming model is based on SYCL, the compilation infrastructure will use LLVM on SPIR-V kernels. For full details please see: http://www.aes.tu-berlin.de/menue/jobs/ Best regards, Biagio Cosenza -- Biagio Cosenza, PhD Senior Researcher Technische Universität Berlin Fakultät IV - Elektrotechnik und Informatik Institut für Te...

Hi all, I'm trying to get the llvm's IR from the source code of Polybench (OMP) https://github.com/cavazos-lab/PolyBench-ACC/tree/master/OpenMP. I noticed a considerable difference between the IR generated using clang -emit-llvm -fopenmp and clang -emit-llvm: * using the -fopenmp flag I get a simplified IR in which I read a single basic block where I can highlight a llvm.memcpy

...C and send it here later on to gather feedback. Extend and Generalize the OpenCL/CUDA Support in Cling --- Cling can incrementally compile CUDA code [7-8] allowing easier set up and enabling some interesting use cases. There are a number of planned improvements including talking to HIP [9] and SYCL to support more hardware architectures. The primary focus of our work is to upstreaming functionality required to build an incremental compiler and rework cling build against vanilla clang and llvm. The last two points are to give the scope of the work which we will be doing the next 2-3 yea...

...g up ICC's "#pragma simd assert" description and see if the assert feature is something you may be interested in seeing as an extended part of LLVM implementation of OpenMP (declare) simd. Else, vectorization report would tell you whether it was vectorized or not. >How does OpenCL/SYCL play in this now? Not right now, when we are working to get OpenMP stuff going --- except that I don't think we need to change the design (e.g., on function attribute, VecClone direction, etc.) in the future for those or similar languages. -----Original Message----- From: Doerfert, Johannes [...