Displaying 2 results from an estimated 2 matches for "swizzle2".
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2007 Sep 27
3
[LLVMdev] Vector swizzling and write masks code generation
...<2 x float> %tmp2, float %tmp3, i32 1
store <2 x float> %tmp4, <2 x float>* @vec2
or the like.
So I think my options come down to:
1) figure out a way of having code generator be actually able to combine all
those IR instructions back into
OP dst.writemask src1.swizzle1 src2.swizzle2
2) have some kind of instruction level support for it in LLVM IR
With my limited knowledge of code generators in LLVM I don't see a way of
doing #1 and I'm afraid #2 might be the only option.
I'd appreciate any ideas and/or comments that could potentially help to solve
this problem....
2007 Sep 27
0
[LLVMdev] Vector swizzling and write masks code generation
...ec4) you can use the shufflevector instruction, but if not,
you have to use insert/extract.
> So I think my options come down to:
>
> 1) figure out a way of having code generator be actually able to combine all
> those IR instructions back into
> OP dst.writemask src1.swizzle1 src2.swizzle2
Yep. If you're using the LLVM code generator, it makes it reasonably easy
to pattern match on this sort of thing and/or introduce machine specific
abstractions to describe them.
-Chris
--
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