Displaying 3 results from an estimated 3 matches for "switchtec".
2019 Feb 18
0
[PATCH] pci/quirks: Add quirk to reset nvgpu at boot for the Lenovo ThinkPad P50
...ble tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v4.20.8, v4.19.21, v4.14.99, v4.9.156, v4.4.174, v3.18.134.
v4.20.8: Build OK!
v4.19.21: Failed to apply! Possible dependencies:
01d5d7fa8376 ("PCI: Add macro for Switchtec quirk declarations")
v4.14.99: Failed to apply! Possible dependencies:
01d5d7fa8376 ("PCI: Add macro for Switchtec quirk declarations")
06dc4ee54e30 ("PCI: Disable MSI for Freescale Layerscape PCIe RC mode")
07f4f97d7b4b ("vga_switcheroo: Use device link f...
2019 Feb 12
7
[PATCH] pci/quirks: Add quirk to reset nvgpu at boot for the Lenovo ThinkPad P50
...ger.kernel.org
---
drivers/pci/quirks.c | 65 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b0a413f3f7ca..948492fda8bf 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5117,3 +5117,68 @@ SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
+
+/*
+ * On certain Lenovo Thinkpad P50 SKUs, specifically those with a Nvidia
+ * Quadro M1000M, the BIOS will occasionally make the...
2018 Aug 31
6
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
...+++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ef7143a274e0..e0d956ee459c 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5119,3 +5119,26 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
quirk_switchtec_ntb_dma_alias);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
quirk_switchtec_ntb_dma_alias);
+
+/*
+ * The Nvidia GPU on many Intel-based Asus products is unusable after
+ * S3 resume. However, for unknown reasons, rewriting the value of register
+ * 'Prefetchable Base Upper 32...