search for: switchinst

Hi, Are there some built-in LLVM transformation pass, or written library code that transforms LLVM::SwitchInst into if-condition statements (LLVM:: BranchInst)? The purpose of the transformation is that we have a legacy program analyzer that includes an LLVM pass manipulating if-condition statements. Statements of LLVM::SwithchInst should have been handled in the same manner but was not done. Thus to trans...

...( BasicBlock* basicBlock, BasicBlock* dispatcherBlock, Value* statePtr, BBindexBBMap& indexBBMap ); static void MovePHINodesToDispatcher( BBindexBBMap& indexBBMap, BasicBlock* dispatcherBB ); static void ConvertSwitch( Function& function ); static BasicBlock* ProcessCase( SwitchInst* switchInst, int caseIdx, BasicBlock* prevBB, Value* testValuePtr ); static void ReduceTempVarsLifetime( Function& function ); static bool IsUsedOutsideParentBlock( Instruction* value ); static const std::string PassName; }; --------------------------------------------- MakeDisp...

I'm trying to figure out how to feed a blockaddress to a switch condition AND destination (basically emulating an indirectbr via a switch; I know it's not a good approach, I'm just experimenting). Suppose I have the following: SwitchInst *s = SwitchInst::Create(...); BasicBlock *bb = ...; PtrToIntInst k = new PtrToIntInst(BlockAddress::get(bb), <TYPE>, "", s); s->addCase(k, bb); ... is this reasonable? what should I put in place of <TYPE> (the type to cast to)? -- Carlo Alberto Ferraris <cafxx at stra...

...at strayorange.com> wrote: > I'm trying to figure out how to feed a blockaddress to a switch condition > AND destination (basically emulating an indirectbr via a switch; I know it's > not a good approach, I'm just experimenting). > Suppose I have the following: > > SwitchInst *s = SwitchInst::Create(...); > BasicBlock *bb = ...; > PtrToIntInst k = new PtrToIntInst(BlockAddress::get(bb), <TYPE>, "", s); > s->addCase(k, bb); > ... > > is this reasonable? what should I put in place of <TYPE> (the type to cast > to)? You can...

Hi, if I want to know how switch instructions are handled in the backend, where do I have to look first? I'm not familiar with the backend framework and I couldn't figure out the interface between the LLVM instruction 'SwitchInst' and whatever there is in the backend. I would be very happy about every hint where I have to look to find the entry point of switch instructions in the backend (in particular in the MIPS backend. Thanks a lot and kind regards, Nico

...wrote: >> I'm trying to figure out how to feed a blockaddress to a switch condition >> AND destination (basically emulating an indirectbr via a switch; I know it's >> not a good approach, I'm just experimenting). >> Suppose I have the following: >> >> SwitchInst *s = SwitchInst::Create(...); >> BasicBlock *bb = ...; >> PtrToIntInst k = new PtrToIntInst(BlockAddress::get(bb),<TYPE>, "", s); >> s->addCase(k, bb); >> ... >> >> is this reasonable? what should I put in place of<TYPE> (the type to cas...

...:52 PM, Nico <listiges at arcor.de> wrote: > Hi, > > if I want to know how switch instructions are handled in the backend, where do I have to look first? > I'm not familiar with the backend framework and I couldn't figure out the interface between the LLVM instruction 'SwitchInst' and whatever there is in the backend. > > I would be very happy about every hint where I have to look to find the entry point of switch instructions in the backend (in particular in the MIPS backend. SelectionDAGBuilder::visitSwitch is the general switch lowering... -Eli

Hi All, Value* V; Value* V2; BasicBlock * BB; unsigned j; ///number of cases .... //insert V , V2, j and BB SwitchInst* sw= builder.CreateSwitch(V, BB, j); ConstantInt * CI= dyn_cast<ConstantInt>(V2); sw-> addCase( CI , BB); At last step there is Program received signal SIGSEGV, Segmentation fault. What is wrong in the code? Thanks in advance -- * Rasha Salah Omar Msc Student at E-JUST...

Moving to LLVM dev to discuss the possibility of extending the cast infrastructure to handle this. On Tue, Nov 20, 2012 at 5:51 PM, John McCall <rjmccall at apple.com> wrote: > On Nov 18, 2012, at 5:05 PM, David Blaikie <dblaikie at gmail.com> wrote: >> TypeLoc casting looks bogus. >> >> TypeLoc derived types return true from classof when the dynamic type >>

Hi I write a LLVM function pass. The pass will loop the basicblock in the function, check the instruction's type with dyn_cast<switchinst>, print the instruction and the basicblock's successors. I think it is not very complex. My bitcode file is about 30M. My CPU is i7-7700(3.6GHz). It has been running for 60 hours but it is still running. I am not sure whether this is a normal behavior. If so, any options or suggestions to h...

...Inst &BI(cast<BranchInst>(I)); + const BranchInst &BI(cast<BranchInst>(I)); Out << ' '; writeOperand(BI.getCondition(), true); Out << ", "; @@ -1769,14 +1769,14 @@ writeOperand(BI.getSuccessor(1), true); } else if (isa<SwitchInst>(I)) { - SwitchInst& SI(cast<SwitchInst>(I)); + const SwitchInst& SI(cast<SwitchInst>(I)); // Special case switch instruction to get formatting nice and correct. Out << ' '; writeOperand(SI.getCondition(), true); Out << ", &q...

Hi all. By now loops with switch instruction are unswitched value-by-value. For example for case range [0..9] we need to run unswitch process 10 times! I want try to optimize that case. Is there any hidden problems that blocks this improvement? Regards, Stepan.

Hi Eli, Thank you for the quick reply. On Feb 27, 2012, at 10:03 PM, Eli Friedman wrote: > SelectionDAGBuilder::visitSwitch is the general switch lowering... I understand this lowering is target independent and there is no additional target dependent handling of switch instructions - right? Only branches and jump tables are left after this lowering? Kind regards, Nico

Hi Rasha, > What is wrong in the code? Your best bet is to run a debugger and see if the variables have values you expect just before that last call, and then look at what's causing the segfault in LLVM (null pointer?) code and work out where the first place it's not doing what you expect is. Cheers. Tim.

...im Target Data Layout Module Pass Manager Function Pass Manager Lower GC intrinsics, for GCless code generators -- Lower GC intrinsics, for GCless code generators Lower invoke and unwind, for unwindless code generators -- Lower invoke and unwind, for unwindless code generators Lower SwitchInst's to branches -- Lower SwitchInst's to branches Remove unreachable blocks from the CFG -- Remove unreachable blocks from the CFG X86 Pattern Instruction Selection -- X86 Pattern Instruction Selection Live Variable Analysis Eliminate PHI nodes for register allocation T...

Hi all, I am slowly working on a SwitchInst optimizer (http://llvm.org/PR8125) and now I am running into a deficiency of the x86 peephole optimizer (or jump-threader?). Here is what I get: andl $3, %edi je .LBB0_4 # BB#2: # %nz # in Loop: H...

...le Pass Manager > Function Pass Manager > Lower GC intrinsics, for GCless code generators > -- Lower GC intrinsics, for GCless code generators > Lower invoke and unwind, for unwindless code generators > -- Lower invoke and unwind, for unwindless code generators > Lower SwitchInst's to branches > -- Lower SwitchInst's to branches > Remove unreachable blocks from the CFG > -- Remove unreachable blocks from the CFG > X86 Pattern Instruction Selection > -- X86 Pattern Instruction Selection > Live Variable Analysis > Eliminate PHI node...

Since a SwitchInst always has a default case even if no default case appeared in the code, what's the best way to determine if it's explicit or implicit? thanks.. don -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161...

...ction Pass Manager > > Lower GC intrinsics, for GCless code generators > > -- Lower GC intrinsics, for GCless code generators > > Lower invoke and unwind, for unwindless code generators > > -- Lower invoke and unwind, for unwindless code generators > > Lower SwitchInst's to branches > > -- Lower SwitchInst's to branches > > Remove unreachable blocks from the CFG > > -- Remove unreachable blocks from the CFG > > X86 Pattern Instruction Selection > > -- X86 Pattern Instruction Selection > > Live Variable Analy...

On Oct 6, 2010, at 6:16 PM, Gabor Greif wrote: > Hi all, > > I am slowly working on a SwitchInst optimizer (http://llvm.org/PR8125) > and now I am running into a deficiency of the x86 > peephole optimizer (or jump-threader?). Here is what I get: > > > andl $3, %edi > je .LBB0_4 > # BB#2: # %nz >...