Displaying 3 results from an estimated 3 matches for "swiftc".
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2015 Oct 05
2
Swift to IR, generates wrong IR
...robably need -emit-bc.
Björn
> ^
>
>> On 05 Oct 2015, at 11:25, Rinaldini Julien via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> Hi,
>> I have a simple swift code from which I generate IR code with ‘swiftc test.swift -emit-ir -o test.ll'
>> When I try to run the .ll file or apply optimization with opt, I get errors like this one:
>>
>> lli: test.ll:548:110: error: expected instruction opcode
>> %9 = cmpxchg i64* bitcast (%swift.type*** @field_type_vector_TipCalculator to...
2015 Oct 05
2
Swift to IR, generates wrong IR
Hi,
I have a simple swift code from which I generate IR code with ‘swiftc test.swift -emit-ir -o test.ll'
When I try to run the .ll file or apply optimization with opt, I get errors like this one:
lli: test.ll:548:110: error: expected instruction opcode
%9 = cmpxchg i64* bitcast (%swift.type*** @field_type_vector_TipCalculator to i64*), i64 0, i64 %8 seq_cst seq_...
2018 Jan 05
0
Question about reg2mem
Greetings,
Lately I have been experimenting on using Obfuscator-llvm on swiftc
bitcode file. During the process of applying the Bogus Control Flow
function pass I encountered the following error:
swifterror value should be the second operand when used by stores
%33 = alloca swifterror %swift.error*, align 8
store %swift.error** %33, %swift.error*** %.reg2mem21
swifterror...