search for: sw_alu0

...ing-point pipeline and a load/store pipeline./ > > /Look into ARM itineraries, they contain a decent amount of such > examples./ > > // > > [Head feb 2013:] > > InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, > > InstrStage<1, [SW_ALU0, SW_ALU1]>], > > [1]>, > > ------------------------------------------------------------------------ > > *From:*Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] > *Sent:* Monday, February 11, 2013 7:19 PM > *To:* Jonas Paulsson; llvmde...

...units from a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples. [Head feb 2013:] InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, InstrStage<1, [SW_ALU0, SW_ALU1]>], [1]>, ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Monday, February 11, 2013 7:19 PM To: Jonas Paulsson; llvmdev at cs.uiuc.edu Subject: RE: DFAPacketizer Jonas, At this point, the D...

Jonas, At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing. -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas

...units from a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples. [Head feb 2013:] InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, InstrStage<1, [SW_ALU0, SW_ALU1]>], [1]>, ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Monday, February 11, 2013 7:19 PM To: Jonas Paulsson; llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: RE: DFAPack...