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...harmful or not ? Here below my rsync command and some of the error messages : rsync --delete -zrv --bwlimit=$bwlimit --timeout=1200 --exclude-from='/etc/rsync/exclude' $user\@" . $server . "::htdocs/$dir/ /var/www/htdocs/$dir/ send_files failed to open www.lft.mg/matieres/svt/Evaluations/CLASSE.GIF: No such file or directory send_files failed to open www.lft.mg/matieres/svt/Evaluations/COUPES.GIF: No such file or directory send_files failed to open www.lft.mg/matieres/svt/Evaluations/DBasalte.gif: No such file or directory send_files failed to open www.lft.mg/matiere...

...ore of a bit convert, store the input value if the // resultant store does not need a higher alignment than the original. if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && ST->isUnindexed()) { unsigned Align = ST->getAlignment(); MVT SVT = Value.getOperand(0).getValueType(); unsigned OrigAlign = TLI.getTargetData()-> getABITypeAlignment(SVT.getTypeForMVT()); if (Align <= OrigAlign && ((!LegalOperations && !ST->isVolatile()) || TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))...

...// resultant store does not need a higher alignment than the original. if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && ST->isUnindexed()) { - unsigned Align = ST->getAlignment(); + unsigned OrigAlign = ST->getAlignment(); MVT SVT = Value.getOperand(0).getValueType(); - unsigned OrigAlign = TLI.getTargetData()-> + unsigned Align = TLI.getTargetData()-> getABITypeAlignment(SVT.getTypeForMVT()); if (Align <= OrigAlign && ((!LegalOperations && !ST->isVolatile()) || Does th...

...urn any type, and in the AMDIL backends case, for a <3 x float>, returns the corresponding integer version of the vector. The problem comes in code like the following(comments removed): This is from DAGCombiner.cpp:visitSIGN_EXTEND. EVT N0VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.g...

...bled. You’ll get more information about what’s going wrong that way. That said, yes, this looks like a bug. Specifically, SelectionDAGLegalize::ExpandConstantFP() assumes that f32 is the smallest floating point constant type it’ll need to handle, and that MVT enum ordering reflects that. while (SVT != MVT::f32) { SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); ... } That function, and possibly others, need to be taught how to handle half-floats, it looks like. -Jim On Jun 17, 2013, at 6:59 AM, Alessio Giovanni B...

...about what’s going wrong that way. > > That said, yes, this looks like a bug. > Specifically, SelectionDAGLegalize::ExpandConstantFP() assumes that f32 is > the smallest floating point constant type it’ll need to handle, and that > MVT enum ordering reflects that. > > while (SVT != MVT::f32) { > > SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); > ... > } > > That function, and possibly others, need to be taught how to handle > half-floats, it looks like. > > -Jim > > On Jun 17, 2013, at 6:59 AM, Alessio Giovanni Baro...

Hi, if I write the following simple program: target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" define void @foo () { %1 = alloca half store half 0xH42CC, half* %1 ; 0xH42CC = 3.4 %2 = load half* %1

...urn any type, and in the AMDIL backends case, for a <3 x float>, returns the corresponding integer version of the vector. The problem comes in code like the following(comments removed): This is from DAGCombiner.cpp:visitSIGN_EXTEND. EVT N0VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.g...

...urn any type, and in the AMDIL backends case, for a <3 x float>, returns the corresponding integer version of the vector. The problem comes in code like the following(comments removed): This is from DAGCombiner.cpp:visitSIGN_EXTEND. EVT N0VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.g...

...sLiveness ... %31:sfgpr32 = ADDrr killed %32:sgpr32, %27:sgpr32 ... Here should not select f32 sfgpr32 register, debugger point to TargetRegisterInfo:: getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT = MVT::SimpleValueType::Any) This function has been called 10+ in LLVM, only one place give specific SVT parameter. Most of those places are hard to get the MVT::SimpleValueType infos and use the default value. That's why sfgpr32 comes out. LLVM defect? - Best Regards, Yu...

...urn any type, and in the AMDIL backends case, for a <3 x float>, returns the corresponding integer version of the vector. The problem comes in code like the following(comments removed): This is from DAGCombiner.cpp:visitSIGN_EXTEND. EVT N0VT = N0.getOperand(0).getValueType(); ... EVT SVT = TLI.getSetCCResultType(N0VT); ... if (VT.getSizeInBits() == SVT.getSizeInBits()) return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), cast<CondCodeSDNode>(N0.getOperand(2))->get()); SVT.g...

...ot need a higher alignment than the original. > if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && > ST->isUnindexed()) { > - unsigned Align = ST->getAlignment(); > + unsigned OrigAlign = ST->getAlignment(); > MVT SVT = Value.getOperand(0).getValueType(); > - unsigned OrigAlign = TLI.getTargetData()-> > + unsigned Align = TLI.getTargetData()-> > getABITypeAlignment(SVT.getTypeForMVT()); > if (Align <= OrigAlign && > ((!LegalOperations && !ST->...

...at way. >> >> That said, yes, this looks like a bug. >> Specifically, SelectionDAGLegalize::ExpandConstantFP() assumes that f32 is >> the smallest floating point constant type it’ll need to handle, and that >> MVT enum ordering reflects that. >> >> while (SVT != MVT::f32) { >> >> SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); >> ... >> } >> >> That function, and possibly others, need to be taught how to handle >> half-floats, it looks like. >> >> -Jim >> >> On Jun...

...;> That said, yes, this looks like a bug. >>> Specifically, SelectionDAGLegalize::ExpandConstantFP() assumes that f32 is >>> the smallest floating point constant type it’ll need to handle, and that >>> MVT enum ordering reflects that. >>> >>> while (SVT != MVT::f32) { >>> >>> SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); >>> ... >>> } >>> >>> That function, and possibly others, need to be taught how to handle >>> half-floats, it looks like. >>> >&g...

...9 (and the current CVS release) from compiling correctly - once again, not sure how to submit, but here are the main things - In SelectionDAGNodes.h StoreSDNode(SDOperand Chain, SDOperand Value, SDOperand Ptr, SDOperand Off, ISD::MemOpAddrMode AM, bool isTrunc, MVT::ValueType SVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) SDOperand Value should really be SDOperand value (lower case), since Value is already a defined classname. Not sure if this is really a 'bug', but it does cause errors in some compilers. Regarding the new stream wr...

...ne_span_data <- as.matrix(read.table('ne_span.data.R.txt', header=TRUE, row.names='id')) library('e1071') svm_ne_span_model <- svm(NE_type ~ . , ne_span_data) it gives me: Error in predict.svm(ret, xhold) : Model is empty! A line from the ne_span.data.R.txt file: svt OTHER N N I S 2 NA NA NA NA NA A NA NA 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 train-s1m2 Any idea what's wrong here? -- View this message in context: http://www.nabble.com/training-svm-tf3296613.html#a9170716 Sent from the R help mailing list archive at Nabble.com...

...gt;> original. >> if (Value.getOpcode() == ISD::BIT_CONVERT && !ST- >> >isTruncatingStore() && >> ST->isUnindexed()) { >> - unsigned Align = ST->getAlignment(); >> + unsigned OrigAlign = ST->getAlignment(); >> MVT SVT = Value.getOperand(0).getValueType(); >> - unsigned OrigAlign = TLI.getTargetData()-> >> + unsigned Align = TLI.getTargetData()-> >> getABITypeAlignment(SVT.getTypeForMVT()); >> if (Align <= OrigAlign && >> ((!LegalOperations &a...

...e [ 0.001000] masked ExtINT on CPU#0 [ 0.001000] ENABLING IO-APIC IRQs [ 0.001000] init IO_APIC IRQs [ 0.001000] apic 8 pin 0 not connected [ 0.001000] IOAPIC[8]: Set IRTE entry (P:1 FPD:0 Dst_Mode:1 Redir_hint:1 Trig_Mode:0 Dlvry_Mode:1 Avail:0 Vector:31 Dest:00000001 SID:F0FF SQ:0 SVT:1) [ 0.001000] IOAPIC[0]: Set routing entry (8-1 -> 0x31 -> IRQ 1 Mode:0 Active:0 Dest:1) [ 0.001000] IOAPIC[8]: Set IRTE entry (P:1 FPD:0 Dst_Mode:1 Redir_hint:1 Trig_Mode:0 Dlvry_Mode:1 Avail:0 Vector:30 Dest:00000001 SID:F0FF SQ:0 SVT:1) [ 0.001000] IOAPIC[0]: Set routing entry (8...

...e [ 0.001000] masked ExtINT on CPU#0 [ 0.001000] ENABLING IO-APIC IRQs [ 0.001000] init IO_APIC IRQs [ 0.001000] apic 8 pin 0 not connected [ 0.001000] IOAPIC[8]: Set IRTE entry (P:1 FPD:0 Dst_Mode:1 Redir_hint:1 Trig_Mode:0 Dlvry_Mode:1 Avail:0 Vector:31 Dest:00000001 SID:F0FF SQ:0 SVT:1) [ 0.001000] IOAPIC[0]: Set routing entry (8-1 -> 0x31 -> IRQ 1 Mode:0 Active:0 Dest:1) [ 0.001000] IOAPIC[8]: Set IRTE entry (P:1 FPD:0 Dst_Mode:1 Redir_hint:1 Trig_Mode:0 Dlvry_Mode:1 Avail:0 Vector:30 Dest:00000001 SID:F0FF SQ:0 SVT:1) [ 0.001000] IOAPIC[0]: Set routing entry (8...

...ipt for the Moran Test (an its LM counterparts) for spatial probit models (Pinkse and Slade (1998) and Kelejian and Prucha (2001)). If someone knows other software that can carry out these estimations I would appreciate it someone could point that out to me. Regards, Jon Fiva (jon.fiva@svt.ntnu.no) Case A.C. 1992. Neighborhood influence and technological change, Regional Science and Urban Economics, 22: 491-508. Kelejian H.H. and Prucha I.R. 2001. On the asymptotic distribution of the Moran I test statistic with applications, Journal of Econometrics, 104: 219-257. Pi...